398 lines
11 KiB
C
398 lines
11 KiB
C
/*
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* Copyright (C) 2010-2019 Fabio Cavallo (aka FHorse)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef CPU_INLINE_H_
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#define CPU_INLINE_H_
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#include <stdlib.h>
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#include "apu.h"
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#include "fds.h"
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#define mod_cycles_op(op, vl) cpu.cycles op vl
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#define r2006_during_rendering()\
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if (!ppu.vblank && r2001.visible && (ppu.frame_y > ppu_sclines.vint) &&\
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(ppu.screen_y < SCR_LINES)) {\
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_r2006_during_rendering()\
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} else {\
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r2006.value += r2000.r2006_inc;\
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}
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#define _r2006_during_rendering()\
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r2006_inc()\
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if ((r2006.value & 0x1F) == 0x1F) {\
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r2006.value ^= 0x41F;\
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} else {\
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r2006.value++;\
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}
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INLINE static void apu_wr_reg(struct NESAPU* a, WORD address, BYTE value) {
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if (!(address & 0x0010)) {
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/* -------------------- square 1 --------------------*/
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if (address <= 0x4003) {
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if (address == 0x4000) {
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square_reg0(a->S1);
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return;
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}
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if (address == 0x4001) {
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square_reg1(a->S1);
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sweep_silence(a->S1)
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return;
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}
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if (address == 0x4002) {
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square_reg2(a->S1);
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sweep_silence(a->S1)
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return;
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}
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if (address == 0x4003) {
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square_reg3(a->S1,a->apu.length_clocked);
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sweep_silence(a->S1)
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return;
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}
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return;
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}
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/* -------------------- square 2 --------------------*/
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if (address <= 0x4007) {
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if (address == 0x4004) {
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square_reg0(a->S2);
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return;
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}
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if (address == 0x4005) {
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square_reg1(a->S2);
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sweep_silence(a->S2)
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return;
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}
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if (address == 0x4006) {
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square_reg2(a->S2);
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sweep_silence(a->S2)
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return;
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}
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if (address == 0x4007) {
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square_reg3(a->S2,a->apu.length_clocked);
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sweep_silence(a->S2)
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return;
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}
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return;
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}
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/* -------------------- triangle --------------------*/
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if (address <= 0x400B) {
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if (address == 0x4008) {
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/* length counter */
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/*
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* il triangle ha una posizione diversa per il
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* flag LCHalt.
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*/
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a->TR.length.halt = value & 0x80;
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/* linear counter */
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a->TR.linear.reload = value & 0x7F;
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return;
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}
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if (address == 0x400A) {
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/* timer (low 8 bits) */
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a->TR.timer = (a->TR.timer & 0x0700) | value;
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return;
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}
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if (address == 0x400B) {
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/* length counter */
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/*
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* se non disabilitato, una scrittura in
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* questo registro, carica immediatamente il
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* length counter del canale, tranne nel caso
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* in cui la scrittura avvenga nello stesso
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* momento del clock di un length counter e
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* con il length diverso da zero.
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*/
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if (a->TR.length.enabled && !(a->apu.length_clocked && a->TR.length.value)) {
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a->TR.length.value = length_table[value >> 3];
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}
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/* timer (high 3 bits) */
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a->TR.timer = (a->TR.timer & 0x00FF) | ((value & 0x07) << 8);
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/*
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* scrivendo in questo registro si setta
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* automaticamente l'halt flag del triangle.
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*/
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a->TR.linear.halt = TRUE;
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return;
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}
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return;
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}
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/* --------------------- noise ----------------------*/
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if (address <= 0x400F) {
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if (address == 0x400C) {
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a->NS.length.halt = value & 0x20;
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/* envelope */
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a->NS.envelope.constant_volume = value & 0x10;
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a->NS.envelope.divider = value & 0x0F;
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return;
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}
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if (address == 0x400E) {
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a->NS.mode = value & 0x80;
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a->NS.timer = value & 0x0F;
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return;
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}
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if (address == 0x400F) {
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/*
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* se non disabilitato, una scrittura in
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* questo registro, carica immediatamente il
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* length counter del canale, tranne nel caso
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* in cui la scrittura avvenga nello stesso
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* momento del clock di un length counter e
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* con il length diverso da zero.
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*/
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if (a->NS.length.enabled && !(a->apu.length_clocked && a->NS.length.value)) {
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a->NS.length.value = length_table[value >> 3];
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}
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/* envelope */
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a->NS.envelope.enabled = TRUE;
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return;
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}
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return;
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}
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return;
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} else {
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/* ---------------------- DMC -----------------------*/
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if (address <= 0x4013) {
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if (address == 0x4010) {
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a->DMC.irq_enabled = value & 0x80;
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/* se l'irq viene disabilitato allora... */
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if (!a->DMC.irq_enabled) {
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/* ...azzero l'interrupt flag del DMC */
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a->r4015.value &= 0x7F;
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}
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a->DMC.loop = value & 0x40;
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a->DMC.rate_index = value & 0x0F;
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return;
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}
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if (address == 0x4011) {
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BYTE save = a->DMC.counter;
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value &= 0x7F;
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/*
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* questa lo faccio perche' in alcuni giochi come Batman,
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* Ninja Gaiden 3, Castlevania II ed altri, producono
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* un popping del suono fastidioso;
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* from Fceu doc:
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* Why do some games make a popping sound (Batman, Ninja Gaiden 3,
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* Castlevania II etc.)? These games do a very crude drum imitation
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* by causing a large jump in the output level for a short period of
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* time via the register at $4011. The analog filters on a real
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* Famicom make it sound decent(better). I have not completely
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* emulated these filters.
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* (Xodnizel)
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*/
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if (a->r4011.frames > 1) {
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a->r4011.output = (value - save) >> 3;
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a->DMC.counter = a->DMC.output = save + a->r4011.output;
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} else {
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a->DMC.counter = a->DMC.output = value;
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}
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a->apu.clocked = TRUE;
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a->r4011.cycles = a->r4011.frames = 0;
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a->r4011.value = value;
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return;
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}
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if (address == 0x4012) {
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a->DMC.address_start = (value << 6) | 0xC000;
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return;
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}
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if (address == 0x4013) {
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/* sample length */
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a->DMC.length = (value << 4) | 0x01;
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return;
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}
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return;
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}
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/* --------------------------------------------------*/
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if (address == 0x4015) {
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/*
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* 76543210
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* || |||||
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* || ||||+- Pulse channel 1's length counter enabled flag
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* || |||+-- Pulse channel 2's length counter enabled flag
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* || ||+--- Triangle channel's length counter enabled flag
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* || |+---- Noise channel's length counter enabled flag
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* || +----- If clear, the DMC's bytes remaining is set to 0,
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* || otherwise the DMC sample is restarted only if the
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* || DMC's bytes remaining is 0
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* |+------- Frame interrupt flag
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* +-------- DMC interrupt flag
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*/
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/*
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* dopo la write il bit 7 (dmc flag) deve
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* essere azzerato mentre lascio inalterati
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* i bit 5 e 6.
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*/
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a->r4015.value = (a->r4015.value & 0x60) | (value & 0x1F);
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/*
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* quando il flag di abilitazione del length
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* counter di ogni canale e' a 0, il counter
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* dello stesso canale e' immediatamente azzerato.
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*/
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if (!(a->S1.length.enabled = a->r4015.value & 0x01)) {
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a->S1.length.value = 0;
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}
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if (!(a->S2.length.enabled = a->r4015.value & 0x02)) {
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a->S2.length.value = 0;
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}
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if (!(a->TR.length.enabled = a->r4015.value & 0x04)) {
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a->TR.length.value = 0;
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}
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if (!(a->NS.length.enabled = a->r4015.value & 0x08)) {
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a->NS.length.value = 0;
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}
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/*
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* se il bit 4 e' 0 allora devo azzerare i bytes
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* rimanenti del DMC, alrimenti devo riavviare
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* la lettura dei sample DMC solo nel caso che
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* in cui i bytes rimanenti siano a 0.
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*/
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if (!(a->r4015.value & 0x10)) {
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a->DMC.remain = 0;
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a->DMC.empty = TRUE;
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} else if (!a->DMC.remain) {
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a->DMC.remain = a->DMC.length;
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a->DMC.address = a->DMC.address_start;
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}
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return;
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}
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#if defined (VECCHIA_GESTIONE_JITTER)
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if (address == 0x4017) {
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/* APU frame counter */
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r4017.jitter.value = value;
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/*
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* nell'2A03 se la scrittura del $4017 avviene
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* in un ciclo pari, allora l'effettiva modifica
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* avverra' nel ciclo successivo.
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*/
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if (cpu.odd_cycle) {
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r4017.jitter.delay = TRUE;
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} else {
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r4017.jitter.delay = FALSE;
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r4017_jitter();
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}
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return;
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}
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#else
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if (address == 0x4017) {
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/* APU frame counter */
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a->r4017.jitter.value = value;
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/*
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* nell'2A03 se la scrittura del $4017 avviene
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* in un ciclo pari, allora l'effettiva modifica
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* avverra' nel ciclo successivo.
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*/
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if (a->apu.odd_cycle) {
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a->r4017.jitter.delay = TRUE;
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} else {
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a->r4017.jitter.delay = FALSE;
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r4017_jitter(1)
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r4017_reset_frame()
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}
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return;
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}
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#endif
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}
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#if defined (DEBUG)
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//fprintf(stderr, "Alert: Attempt to write APU port %04X\n", address);
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#endif
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return;
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}
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INLINE static BYTE fds_wr_mem(struct _fds* fds, WORD address, BYTE value) {
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if (address == 0x4023) {
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fds->enabled_snd_reg=value&0x02;
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}
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if ((address >= 0x4040) && (address <= 0x408A)) {
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if (fds->enabled_snd_reg) {
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if ((address >= 0x4040) && (address <= 0x407F)) {
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fds->snd.wave.data[address & 0x003F] = value & 0x3F;
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return (TRUE);
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}
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if (address == 0x4080) {
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fds->snd.volume.speed = value & 0x3F;
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fds->snd.volume.increase = value & 0x40;
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fds->snd.volume.mode = value & 0x80;
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return (TRUE);
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}
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if (address == 0x4082) {
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fds->snd.main.frequency = (fds->snd.main.frequency & 0xFF00) | value;
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return (TRUE);
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}
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if (address == 0x4083) {
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fds->snd.main.frequency = ((value & 0x0F) << 8) | (fds->snd.main.frequency & 0x00FF);
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fds->snd.envelope.disabled = value & 0x40;
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fds->snd.main.silence = value & 0x80;
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return (TRUE);
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}
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if (address == 0x4084) {
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fds->snd.sweep.speed = value & 0x3F;
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fds->snd.sweep.increase = value & 0x40;
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fds->snd.sweep.mode = value & 0x80;
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return (TRUE);
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}
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if (address == 0x4085) {
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fds->snd.sweep.bias = ((SBYTE) (value << 1)) / 2;
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fds->snd.modulation.index = 0;
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return (TRUE);
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}
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if (address == 0x4086) {
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fds->snd.modulation.frequency = (fds->snd.modulation.frequency & 0xFF00) | value;
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return (TRUE);
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}
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if (address == 0x4087) {
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fds->snd.modulation.frequency = ((value & 0x0F) << 8)
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| (fds->snd.modulation.frequency & 0x00FF);
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fds->snd.modulation.disabled = value & 0x80;
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return (TRUE);
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}
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if (address == 0x4088) {
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BYTE i;
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// 0,2,4,6,-8,-6,-4,-2
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for (i = 0; i < 32; i++) {
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BYTE a = i << 1;
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if (i < 31) {
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fds->snd.modulation.data[a] = fds->snd.modulation.data[a + 2];
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} else {
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BYTE tmp = ((value & 0x03) | (0x3F * (value & 0x04)));
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fds->snd.modulation.data[a] = (SBYTE) tmp;
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}
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fds->snd.modulation.data[a + 1] = fds->snd.modulation.data[a];
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}
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return (TRUE);
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}
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if (address == 0x4089) {
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fds->snd.wave.writable = value & 0x80;
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fds->snd.wave.volume = value & 0x03;
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return (TRUE);
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}
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if (address == 0x408A) {
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fds->snd.envelope.speed = value;
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return (TRUE);
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}
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}
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}
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return (FALSE);
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}
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#endif /* CPU_INLINE_H_ */
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