411 lines
16 KiB
PHP
411 lines
16 KiB
PHP
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; MOS6502/6510/8500/8502
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.ifndef _CPU_INC_
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_CPU_INC_ = 1
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.ifndef PLATFORM
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PLATFORM = 64
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.endif
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.if PLATFORM = 16
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CLOCK_PAL = 886723; Hz - single clock
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.define CYCLES_PER_SECOND_PAL .byte $c3, $87, $0d, $00; 886723 - single clock
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CLOCK_NTSC = 894886; Hz - single clock
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.define CYCLES_PER_SECOND_NTSC .byte $a6, $a7, $0d, $00; 894886 - single clock
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.else
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CLOCK_PAL = 985248; Hz
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.define CYCLES_PER_SECOND_PAL .byte $a0, $08, $0f, $00; 985248
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CLOCK_NTSC = 1022727; Hz
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.define CYCLES_PER_SECOND_NTSC .byte $07, $9b, $0f, $00; 1022727
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.endif
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OPC_BRK = $00
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OPC_ORA_ZPXI = $01
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OPC_JAM = $02; unofficial
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OPC_SLO_ZPXI = $03; unofficial
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;OPC_NOP = $04; unofficial
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OPC_ORA_ZP = $05
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OPC_ASL_ZP = $06
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OPC_SLO_ZP = $07; unofficial
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OPC_PHP = $08
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OPC_ORA_IMM = $09
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OPC_ASL = $0a
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OPC_ANC_IMM = $0b; unofficial
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OPC_NOP_ABS = $0c
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OPC_ORA_ABS = $0d
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OPC_ASL_ABS = $0e
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OPC_SLO_ABS = $0f; unofficial
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OPC_BPL = $10
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OPC_ORA_ZPIY = $11
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;OPC_JAM = $12; unofficial
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OPC_SLO_ZPIY = $13; unofficial
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OPC_NOP_ZPX = $14; unofficial
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OPC_ORA_ZPX = $15
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OPC_ASL_ZPX = $16
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OPC_SLO_ZPX = $17; unofficial
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OPC_CLC = $18
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OPC_ORA_ABSY = $19
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;OPC_NOP = $1a; unofficial
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OPC_SLO_ABSY = $1b; unofficial
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OPC_NOP_ABSX = $1c; unofficial
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OPC_ORA_ABSX = $1d
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OPC_ASL_ABSX = $1e
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OPC_SLO_ABSX = $1f; unofficial
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OPC_JSR_ABS = $20
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OPC_AND_ZPXI = $21
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;OPC_JAM = $22; unofficial
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OPC_RLA_ZPXI = $23; unofficial
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OPC_BIT_ZP = $24
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OPC_AND_ZP = $25
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OPC_ROL_ZP = $26
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OPC_RLA_ZP = $27; unofficial
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OPC_PLP = $28
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OPC_AND_IMM = $29
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OPC_ROL = $2a
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;OPC_ANC_IMM = $2b; unofficial
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OPC_BIT_ABS = $2c
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OPC_AND_ABS = $2d
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OPC_ROL_ABS = $2e
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OPC_RLA_ABS = $2f; unofficial
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OPC_BMI = $30
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OPC_AND_ZPIY = $31
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;OPC_JAM = $32; unofficial
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OPC_RLA_ZPIY = $33; unofficial
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;OPC_NOP_ZPX = $34
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OPC_AND_ZPX = $35
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OPC_ROL_ZPX = $36
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OPC_RLA_ZPX = $37; unofficial
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OPC_SEC = $38
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OPC_AND_ABSY = $39
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;OPC_NOP = $3a; unofficial
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OPC_RLA_ABSY = $3b; unofficial
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;OPC_NOP_ABSX = $3c
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OPC_AND_ABSX = $3d
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OPC_ROL_ABSX = $3e
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OPC_RLA_ABSX = $3f; unofficial
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OPC_RTI = $40
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OPC_EOR_ZPXI = $41
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;OPC_JAM = $42; unofficial
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OPC_SRE_ZPXI = $43; unofficial
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OPC_NOP_ZP = $44
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OPC_EOR_ZP = $45
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OPC_LSR_ZP = $46
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OPC_SRE_ZP = $47; unofficial
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OPC_PHA = $48
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OPC_EOR_IMM = $49
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OPC_LSR = $4a
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OPC_ASL_IMM = $4b
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OPC_JMP_ABS = $4c
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OPC_EOR_ABS = $4d
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OPC_LSR_ABS = $4e
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OPC_SRE_ABS = $4f; unofficial
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OPC_BVC = $50
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OPC_EOR_ZPIY = $51
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;OPC_JAM = $52; unofficial
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OPC_SRE_ZPIY = $53; unofficial
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;OPC_NOP_ZPX = $54; unofficial
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OPC_EOR_ZPX = $55
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OPC_LSR_ZPX = $56
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OPC_SRE_ZPX = $57; unofficial
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OPC_CLI = $58
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OPC_EOR_ABSY = $59
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;OPC_NOP = $5a
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OPC_SRE_ABSY = $5b; unofficial
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;OPC_NOP_ABSX = $5c
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OPC_EOR_ABSX = $5d
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OPC_LSR_ABSX = $5e
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OPC_SRE_ABSX = $5f; unofficial
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OPC_RTS = $60
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OPC_ADC_ZPIX = $61
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;OPC_JAM = $62; unofficial
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OPC_RRA_ZPIX = $63; unofficial
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;OPC_NOP_ZP = $64; unofficial
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OPC_ADC_ZP = $65
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OPC_ROR_ZP = $66
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OPC_RRA_ZP = $67; unofficial
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OPC_PLA = $68
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OPC_ADC_IMM = $69
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OPC_ROR = $6a
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OPC_ARR_IMM = $6b; unofficial
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OPC_JMP_ABSI = $6c
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OPC_ADC_ABS = $6d
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OPC_ROR_ABS = $6e
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OPC_RRA_ABS = $6f; unofficial
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OPC_BVS = $70
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OPC_ADC_ZPIY = $71
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;OPC_JAM = $72; unofficial
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OPC_RRA_ZPIY = $73; unofficial
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;OPC_NOP_ZPX = $74; unofficial
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OPC_ADC_ZPX = $75
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OPC_ROR_ZPX = $76
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OPC_RRA_ZPX = $77; unofficial
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OPC_SEI = $78
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OPC_ADC_ABSY = $79
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;OPC_NOP = $7a; unofficial
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OPC_RRA_ABSY = $7b; unofficial
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;OPC_NOP_ABSX = $7c; unofficial
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OPC_ADC_ABSX = $7d
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OPC_ROR_ABSX = $7e
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OPC_RRA_ABSX = $7f; unofficial
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OPC_NOP_IMM = $80; unofficial
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OPC_STA_ZPXI = $81
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;OPC_NOP_IMM = $82
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OPC_SAX_ZPXI = $83; unofficial
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OPC_STY_ZP = $84
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OPC_STA_ZP = $85
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OPC_STX_ZP = $86
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OPC_SAX_ZP = $87; unofficial
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OPC_DEY = $88
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;OPC_NOP_IMM = $89; unofficial
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OPC_TXA = $8a
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OPC_XAA_IMM = $8b; unofficial
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OPC_STY_ABS = $8c
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OPC_STA_ABS = $8d
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OPC_STX_ABS = $8e
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OPC_SAX_ABS = $8f; unofficial
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OPC_BCC = $90
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OPC_STA_ZPIY = $91
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;OPC_JAM = $92; unofficial
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OPC_AHX_ZPIY = $93; unofficial
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OPC_STY_ZPX = $94
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OPC_STA_ZPX = $95
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OPC_STY_ZPY = $96
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OPC_SAX_ZPY = $97; unofficial
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OPC_TYA = $98
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OPC_STA_ABSY = $99
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OPC_TXS = $9a
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OPC_TAS_ABSY = $9b; unofficial
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OPC_SHF_ABSX = $9c; unofficial
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OPC_STA_ABSX = $9d
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OPC_SHX_ABSY = $9e; unofficial
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OPC_AHX_ABSY = $9f; unofficial
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OPC_LDY_IMM = $a0
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OPC_LDA_ZPXI = $a1
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OPC_LDX_IMM = $a2
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OPC_LAX_ZPXI = $a3; unofficial
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OPC_LDY_ZP = $a4
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OPC_LDA_ZP = $a5
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OPC_LDX_ZP = $a6
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OPC_LAX_ZP = $a7
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OPC_TAY = $a8
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OPC_LDA_IMM = $a9
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OPC_TAX = $aa
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OPC_LAX_IMM = $ab; unofficial
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OPC_LDY_ABS = $ac
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OPC_LDA_ABS = $ad
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OPC_LDX_ABS = $ae
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OPC_LAX_ABS = $af; unofficial
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OPC_BCS = $b0
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OPC_LDA_ZPIY = $b1
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;OPC_JAM = $b2; unofficial
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;OPC_LAX_ZPI = $b3; unofficial
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OPC_LDY_ZPX = $b4
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OPC_LDA_ZPX = $b5
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OPC_LDX_ZPY = $b6
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OPC_LAX_ZPY = $b7; unofficial
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OPC_CLV = $b8
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OPC_LDA_ABSY = $b9
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OPC_TSX = $ba
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OPC_LAS_ABSY = $bb
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OPC_LDY_ABSX = $bc
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OPC_LDA_ABSX = $bd
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OPC_LDX_ABSY = $be
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OPC_LAX_ABSY = $bf; unofficial
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OPC_CPY_IMM = $c0
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OPC_CMP_ZPXI = $c1
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;OPC_NOP_IMM = $c2; unofficial
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OPC_DCP_ZPXI = $c3; unofficial
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OPC_CPY_ZP = $c4
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OPC_CMP_ZP = $c5
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OPC_DEC_ZP = $c6
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OPC_DCP_ZP = $c7; unofficial
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OPC_INY = $c8
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OPC_CMP_IMM = $c9
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OPC_DEX = $ca
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OPC_SBX_IMM = $cb; unofficial
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OPC_CPY_ABS = $cc
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OPC_CMP_ABS = $cd
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OPC_DEC_ABS = $ce
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OPC_DCP_ABS = $cf; unofficial
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OPC_BNE = $d0
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OPC_CMP_ZPIY = $d1
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;OPC_JAM = $d2; unofficial
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OPC_DCP_ZPIY = $d3; unofficial
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;OPC_NOP_ZPX = $d4; unofficial
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OPC_CMP_ZPX = $d5
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OPC_DEC_ZPX = $d6
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OPC_DCP_ZPX = $d7; unofficial
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OPC_CLD = $d8
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OPC_CMP_ABSY = $d9
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;OPC_NOP = $da; unofficial
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OPC_DCP_ABSY = $db; unofficial
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;OPC_NOP_ABSX = $dc; unofficial
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OPC_CMP_ABSX = $dd
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OPC_DEC_ABSX = $de
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OPC_DCP_ABSX = $df; unofficial
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OPC_CPX_IMM = $e0
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OPC_SBC_ZPXI = $e1
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;OPC_NOP_IMM = $e2; unofficial
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OPC_ISC_ZPXI = $e3; unofficial
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OPC_CPX_ZP = $e4
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OPC_SBC_ZP = $e5
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OPC_INC_ZP = $e6
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OPC_ISC_ZP = $e7; unofficial
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OPC_INX = $e8
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OPC_SBC_IMM = $e9
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OPC_NOP = $ea
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;OPC_SBC_IMM = $eb
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OPC_CPX_ABS = $ec
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OPC_SBC_ABS = $ed
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OPC_INC_ABS = $ee
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OPC_ISC_ABS = $ef; unofficial
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OPC_BEQ = $f0
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OPC_SBC_ZPIY = $f1
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;OPC_JAM = $f2; unofficial
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OPC_ISC_ZPIY = $f3; unofficial
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;OPC_NOP_ZPX = $f4; unofficial
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OPC_SBC_ZPX = $f5
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OPC_INC_ZPX = $f6
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OPC_ISC_ZPX = $f7; unofficial
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OPC_SED = $f8
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OPC_SBC_ABSY = $f9
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;OPC_NOP = $fa; unofficial
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OPC_ISC_ABSY = $fb; unofficial
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;OPC_NOP_ABSX = $fc; unofficial
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OPC_SBC_ABSX = $fd
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OPC_INC_ABSX = $fe
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OPC_ISC_ABSX = $ff; unofficial
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NEGATIVE = $80; N flag
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OVERFLOW = $40; V flag
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BREAK = $10; B flag
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DECIMAL = $08; D flag
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INTERRUPT = $04; I flag
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ZERO = $02; Z flag
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CARRY = $01; C flag
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FLAG_N = $80; N flag
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FLAG_V = $40; V flag
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FLAG_B = $10; B flag
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FLAG_D = $08; D flag
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FLAG_I = $04; I flag
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FLAG_Z = $02; Z flag
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FLAG_C = $01; C flag
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IO_PORT_DIRECTION = $00
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.if PLATFORM = 16
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IO_PORT_SERIAL_DATA_OUT_OUTPUT = %00000001
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IO_PORT_SERIAL_DATA_OUT_INPUT = %00000000
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IO_PORT_SERIAL_CLK_OUT_OUTPUT = %00000010
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IO_PORT_SERIAL_CLK_OUT_INPUT = %00000000
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IO_PORT_SERIAL_ATN_OUT_OUTPUT = %00000100
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IO_PORT_SERIAL_ATN_OUT_INPUT = %00000000
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IO_PORT_CST_MTR_OUTPUT = %00001000
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IO_PORT_CST_MTR_INPUT = %00000000
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IO_PORT_CST_RD_OUTPUT = %00010000
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IO_PORT_CST_RD_INPUT = %00000000
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IO_PORT_SERIAL_CLK_IN_OUTPUT = %01000000
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IO_PORT_SERIAL_CLK_IN_INPUT = %00000000
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IO_PORT_CST_WRT_INPUT = IO_PORT_SERIAL_CLK_IN_INPUT
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IO_PORT_CST_WRT_OUTPUT = IO_PORT_SERIAL_CLK_IN_OUTPUT
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IO_PORT_SERIAL_DATA_IN_OUTPUT = %10000000
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IO_PORT_SERIAL_DATA_IN_INPUT = %00000000
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IO_PORT_CST_SENSE_INPUT = IO_PORT_SERIAL_DATA_IN_INPUT
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IO_PORT_CST_SENSE_OUTPUT = IO_PORT_SERIAL_DATA_IN_OUTPUT
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.else
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LORAM_OUTPUT = %00000001
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LORAM_INPUT = %00000000
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HIRAM_OUTPUT = %00000010
|
||
|
|
HIRAM_INPUT = %00000000
|
||
|
|
CHAREN_OUTPUT = %00000100
|
||
|
|
CHAREN_INPUT = %00000000
|
||
|
|
CASSETTE_WRITE_OUTPUT = %00001000
|
||
|
|
CASSETTE_WRITE_INPUT = %00000000
|
||
|
|
CASSETTE_SENSE_OUTPUT = %00010000
|
||
|
|
CASSETTE_SENSE_INPUT = %00000000
|
||
|
|
CASSETTE_MOTOR_OUTPUT = %00100000
|
||
|
|
CASSETTE_MOTOR_INPUT = %00000000
|
||
|
|
|
||
|
|
IO_PORT_DIRECTION_DEFAULT = CASSETTE_MOTOR_OUTPUT | CASSETTE_SENSE_OUTPUT | CASSETTE_WRITE_OUTPUT | CHAREN_OUTPUT | HIRAM_OUTPUT | LORAM_OUTPUT
|
||
|
|
.endif
|
||
|
|
|
||
|
|
IO_PORT = $01
|
||
|
|
.if PLATFORM = 16
|
||
|
|
IO_PORT_SERIAL_DATA_OUT = %00000001
|
||
|
|
IO_PORT_CST_SENSE_OUT = %00000001
|
||
|
|
IO_PORT_SERIAL_CLK_OUT = %00000010
|
||
|
|
IO_PORT_CST_WRT_OUT = %00000010
|
||
|
|
IO_PORT_SERIAL_ATN_OUT = %00000100
|
||
|
|
IO_PORT_CST_MTR = %00001000
|
||
|
|
IO_PORT_CST_MTR_OFF = IO_PORT_CST_MTR
|
||
|
|
IO_PORT_CST_MTR_ON = %00000000
|
||
|
|
IO_PORT_CST_RD = %00010000
|
||
|
|
IO_PORT_SERIAL_CLK_IN = %01000000
|
||
|
|
IO_PORT_CST_WRT_IN = %01000000
|
||
|
|
IO_PORT_SERIAL_DATA_IN = %10000000
|
||
|
|
IO_PORT_CST_SENSE_IN = %10000000
|
||
|
|
.else
|
||
|
|
CASSETTE_WRITE = %00001000
|
||
|
|
CASSETTE_SENSE = %00010000
|
||
|
|
CASSETTE_MOTOR = %00100000
|
||
|
|
.if PLATFORM = 128
|
||
|
|
CPU_D800_BANK_0 = %00000000
|
||
|
|
CPU_D800_BANK_1 = %00000001
|
||
|
|
VIC_D800_BANK_0 = %00000000
|
||
|
|
VIC_D800_BANK_1 = %00000010
|
||
|
|
CHARGEN_ENABLED = %00000000
|
||
|
|
CHARGEN_DISABLED = %00000100
|
||
|
|
CAPS_LOCK_OFF = %01000000; ASCII for German C-128
|
||
|
|
CAPS_LOCK_ON = %00000000; DIN for German C-128
|
||
|
|
|
||
|
|
IO_PORT_CHARGEN_ENABLED = CAPS_LOCK_OFF | CASSETTE_SENSE | CASSETTE_MOTOR | CHARGEN_ENABLED | VIC_D800_BANK_1 | CPU_D800_BANK_1; $77
|
||
|
|
IO_PORT_CHARGEN_DISABLED = CAPS_LOCK_OFF | CASSETTE_SENSE | CASSETTE_MOTOR | CHARGEN_DISABLED | VIC_D800_BANK_1 | CPU_D800_BANK_1; $73
|
||
|
|
|
||
|
|
.else
|
||
|
|
LORAM = %00000001
|
||
|
|
HIRAM = %00000010
|
||
|
|
CHAREN = %00000100
|
||
|
|
|
||
|
|
MEMCONFIG_IO_KERNAL_BASIC = CASSETTE_SENSE | CASSETTE_MOTOR | CHAREN | HIRAM | LORAM; $37
|
||
|
|
MEMCONFIG_IO_KERNAL = CASSETTE_SENSE | CASSETTE_MOTOR | CHAREN | HIRAM | 0 ; $36
|
||
|
|
MEMCONFIG_IO = CASSETTE_SENSE | CASSETTE_MOTOR | CHAREN | 0 | LORAM; $35
|
||
|
|
MEMCONFIG_ALL_RAM_2 = CASSETTE_SENSE | CASSETTE_MOTOR | CHAREN | 0 | 0 ; $34
|
||
|
|
MEMCONFIG_CHARGEN_KERNAL_BASIC = CASSETTE_SENSE | CASSETTE_MOTOR | 0 | HIRAM | LORAM; $33
|
||
|
|
MEMCONFIG_CHARGEN_KERNAL = CASSETTE_SENSE | CASSETTE_MOTOR | 0 | HIRAM | 0 ; $32
|
||
|
|
MEMCONFIG_CHARGEN = CASSETTE_SENSE | CASSETTE_MOTOR | 0 | 0 | LORAM; $31
|
||
|
|
MEMCONFIG_ALL_RAM = CASSETTE_SENSE | CASSETTE_MOTOR | 0 | 0 | 0 ; $30
|
||
|
|
.endif
|
||
|
|
.endif
|
||
|
|
|
||
|
|
STACK = $0100
|
||
|
|
|
||
|
|
NMI_VECTOR = $fffa
|
||
|
|
NMI_VECTORLO = $fffa
|
||
|
|
NMI_VECTORHI = $fffb
|
||
|
|
|
||
|
|
RESET_VECTOR = $fffc
|
||
|
|
RESET_VECTORLO = $fffc
|
||
|
|
RESET_VECTORHI = $fffd
|
||
|
|
|
||
|
|
IRQ_VECTOR = $fffe
|
||
|
|
IRQ_VECTORLO = $fffe
|
||
|
|
IRQ_VECTORHI = $ffff
|
||
|
|
|
||
|
|
.macro SKIPBYTE
|
||
|
|
.byte OPC_BIT_ZP
|
||
|
|
.endmacro
|
||
|
|
|
||
|
|
.macro SKIPBYTE_NOP
|
||
|
|
.byte OPC_NOP_IMM
|
||
|
|
.endmacro
|
||
|
|
|
||
|
|
.macro SKIPWORD
|
||
|
|
.byte OPC_BIT_ABS
|
||
|
|
.endmacro
|
||
|
|
|
||
|
|
.macro SKIPWORD_NOP
|
||
|
|
.byte OPC_NOP_ABS
|
||
|
|
.endmacro
|
||
|
|
|
||
|
|
.endif; !_CPU_INC_
|