415 lines
10 KiB
C++
415 lines
10 KiB
C++
// license:BSD-3-Clause
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// copyright-holders:Couriersud
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#ifndef MAME_SOUND_AY8910_H
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#define MAME_SOUND_AY8910_H
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#pragma once
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#include <algorithm>
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#define ALL_8910_CHANNELS -1
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/* Internal resistance at Volume level 7. */
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#define AY8910_INTERNAL_RESISTANCE (356)
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#define YM2149_INTERNAL_RESISTANCE (353)
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/*
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* The following is used by all drivers not reviewed yet.
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* This will like the old behavior, output between
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* 0 and 7FFF
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*/
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#define AY8910_LEGACY_OUTPUT (0x01)
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/*
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* Specifying the next define will simulate the special
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* cross channel mixing if outputs are tied together.
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* The driver will only provide one stream in this case.
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*/
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#define AY8910_SINGLE_OUTPUT (0x02)
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/*
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* The following define is the default behavior.
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* Output level 0 is 0V and 7ffff corresponds to 5V.
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* Use this to specify that a discrete mixing stage
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* follows.
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*/
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#define AY8910_DISCRETE_OUTPUT (0x04)
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/*
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* The following define causes the driver to output
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* resistor values. Intended to be used for
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* netlist interfacing.
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*/
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#define AY8910_RESISTOR_OUTPUT (0x08)
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/*
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* This define specifies the initial state of
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* YM2149, YM3439, AY8930 pin 26 (SEL pin).
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* By default it is set to high,
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* compatible with AY8910.
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*/
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/* TODO: make it controllable while it's running (used by any hw???) */
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#define YM2149_PIN26_HIGH (0x00) /* or N/C */
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#define YM2149_PIN26_LOW (0x10)
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#define BIT(x,n) (((x)>>(n))&1)
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enum device_type {
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AY8910,
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AY8912,
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AY8913,
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AY8914,
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AY8930,
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YM2149,
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YM3439,
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YMZ284,
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YMZ294,
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SUNSOFT_5B_SOUND
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};
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class ay8910_device
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{
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public:
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enum psg_type_t
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{
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PSG_TYPE_AY,
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PSG_TYPE_YM
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};
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enum config_t
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{
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PSG_DEFAULT = 0x0,
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PSG_PIN26_IS_CLKSEL = 0x1,
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PSG_HAS_INTERNAL_DIVIDER = 0x2,
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PSG_EXTENDED_ENVELOPE = 0x4,
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PSG_HAS_EXPANDED_MODE = 0x8
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};
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// construction/destruction
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ay8910_device(unsigned int clock);
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// configuration helpers
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void set_flags(int flags) { m_flags = flags; }
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void set_psg_type(psg_type_t psg_type) { set_type(psg_type, m_flags & YM2149_PIN26_LOW); }
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void set_psg_type(psg_type_t psg_type, bool clk_sel) { set_type(psg_type, clk_sel); }
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void set_resistors_load(int res_load0, int res_load1, int res_load2) { m_res_load[0] = res_load0; m_res_load[1] = res_load1; m_res_load[2] = res_load2; }
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unsigned char data_r() { return ay8910_read_ym(); }
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void address_w(unsigned char data);
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void data_w(unsigned char data);
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// /RES
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void reset_w(unsigned char data = 0) { ay8910_reset_ym(); }
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// Clock select pin
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void set_clock_sel(bool clk_sel)
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{
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if (m_feature & PSG_PIN26_IS_CLKSEL)
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{
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if (clk_sel)
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m_flags |= YM2149_PIN26_LOW;
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else
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m_flags &= ~YM2149_PIN26_LOW;
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m_step_mul = is_clock_divided() ? 2 : 1;
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m_env_step_mul = (!(m_feature & PSG_HAS_EXPANDED_MODE)) && (m_type == PSG_TYPE_AY) ? (m_step_mul << 1) : m_step_mul;
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if (m_feature & PSG_HAS_EXPANDED_MODE)
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m_env_step_mul <<= 1;
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}
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}
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// use this when BC1 == A0; here, BC1=0 selects 'data' and BC1=1 selects 'latch address'
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void data_address_w(int offset, unsigned char data) { ay8910_write_ym(~offset & 1, data); } // note that directly connecting BC1 to A0 puts data on 0 and address on 1
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// use this when BC1 == !A0; here, BC1=0 selects 'latch address' and BC1=1 selects 'data'
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void address_data_w(int offset, unsigned char data) { ay8910_write_ym(offset & 1, data); }
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// bc1=a0, bc2=a1
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void write_bc1_bc2(int offset, unsigned char data);
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struct ay_ym_param
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{
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double r_up;
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double r_down;
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int res_count;
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double res[32];
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};
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struct mosfet_param
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{
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double m_Vth;
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double m_Vg;
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int m_count;
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double m_Kn[32];
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};
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int lastIndx;
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// internal interface for PSG component of YM device
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// FIXME: these should be private, but vector06 accesses them directly
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ay8910_device(device_type type, unsigned int clock, psg_type_t psg_type, int streams, int ioports, int feature = PSG_DEFAULT, bool clk_sel = false);
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// device-level overrides
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void device_start();
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void device_reset();
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// sound stream update overrides
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void sound_stream_update(short** outputs, int outLen);
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void ay8910_write_ym(int addr, unsigned char data);
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unsigned char ay8910_read_ym();
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void ay8910_reset_ym();
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private:
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static constexpr int NUM_CHANNELS = 3;
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device_type chip_type;
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/* register id's */
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enum
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{
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AY_AFINE = 0x00,
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AY_ACOARSE = 0x01,
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AY_BFINE = 0x02,
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AY_BCOARSE = 0x03,
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AY_CFINE = 0x04,
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AY_CCOARSE = 0x05,
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AY_NOISEPER = 0x06,
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AY_ENABLE = 0x07,
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AY_AVOL = 0x08,
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AY_BVOL = 0x09,
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AY_CVOL = 0x0a,
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AY_EAFINE = 0x0b,
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AY_EACOARSE = 0x0c,
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AY_EASHAPE = 0x0d,
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AY_PORTA = 0x0e,
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AY_PORTB = 0x0f,
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AY_EBFINE = 0x10,
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AY_EBCOARSE = 0x11,
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AY_ECFINE = 0x12,
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AY_ECCOARSE = 0x13,
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AY_EBSHAPE = 0x14,
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AY_ECSHAPE = 0x15,
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AY_ADUTY = 0x16,
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AY_BDUTY = 0x17,
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AY_CDUTY = 0x18,
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AY_NOISEAND = 0x19,
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AY_NOISEOR = 0x1a,
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AY_TEST = 0x1f
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};
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// structs
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struct tone_t
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{
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unsigned int period;
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unsigned char volume;
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unsigned char duty;
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int count;
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unsigned char duty_cycle;
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unsigned char output;
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void reset()
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{
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period = 1;
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volume = 0;
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duty = 0;
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count = 0;
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duty_cycle = 0;
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output = 0;
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}
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void set_period(unsigned char fine, unsigned char coarse)
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{
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period = std::max<unsigned int>(1, fine | (coarse << 8));
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}
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void set_volume(unsigned char val)
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{
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volume = val;
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}
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void set_duty(unsigned char val)
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{
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duty = val;
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}
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};
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struct envelope_t
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{
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unsigned int period;
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int count;
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signed char step;
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unsigned int volume;
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unsigned char hold, alternate, attack, holding;
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void reset()
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{
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period = 1;
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count = 0;
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step = 0;
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volume = 0;
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hold = 0;
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alternate = 0;
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attack = 0;
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holding = 0;
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}
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void set_period(unsigned char fine, unsigned char coarse)
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{
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period = std::max<unsigned int>(1, fine | (coarse << 8));
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}
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void set_shape(unsigned char shape, unsigned char mask)
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{
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attack = (shape & 0x04) ? mask : 0x00;
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if ((shape & 0x08) == 0)
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{
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/* if Continue = 0, map the shape to the equivalent one which has Continue = 1 */
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hold = 1;
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alternate = attack;
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}
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else
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{
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hold = shape & 0x01;
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alternate = shape & 0x02;
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}
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step = mask;
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holding = 0;
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volume = (step ^ attack);
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}
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};
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inline void noise_rng_tick()
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{
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// The Random Number Generator of the 8910 is a 17-bit shift
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// register. The input to the shift register is bit0 XOR bit3
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// (bit0 is the output). This was verified on AY-3-8910 and YM2149 chips.
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if (m_feature & PSG_HAS_EXPANDED_MODE) // AY8930 LFSR algorithm is slightly different, verified from manual
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m_rng = (m_rng >> 1) | ((BIT(m_rng, 0) ^ BIT(m_rng, 2)) << 16);
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else
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m_rng = (m_rng >> 1) | ((BIT(m_rng, 0) ^ BIT(m_rng, 3)) << 16);
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}
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// inlines
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inline bool tone_enable(int chan) { return BIT(m_regs[AY_ENABLE], chan); }
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inline unsigned char tone_volume(tone_t *tone) { return tone->volume & (is_expanded_mode() ? 0x1f : 0x0f); }
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inline unsigned char tone_envelope(tone_t *tone) { return (tone->volume >> (is_expanded_mode() ? 5 : 4)) & ((m_feature & PSG_EXTENDED_ENVELOPE) ? 3 : 1); }
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inline unsigned char tone_duty(tone_t *tone) { return is_expanded_mode() ? (tone->duty & 0x8 ? 0x8 : (tone->duty & 0xf)) : 0x4; }
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inline unsigned char get_envelope_chan(int chan) { return is_expanded_mode() ? chan : 0; }
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inline bool noise_enable(int chan) { return BIT(m_regs[AY_ENABLE], 3 + chan); }
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inline unsigned char noise_period() { return std::max<unsigned char>(1, is_expanded_mode() ? (m_regs[AY_NOISEPER] & 0xff) : (m_regs[AY_NOISEPER] & 0x1f)); }
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inline unsigned char noise_output() { return is_expanded_mode() ? m_noise_out & 1 : m_rng & 1; }
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inline bool is_expanded_mode() { return ((m_feature & PSG_HAS_EXPANDED_MODE) && ((m_mode & 0xe) == 0xa)); }
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inline unsigned char get_register_bank() { return is_expanded_mode() ? (m_mode & 0x1) << 4 : 0; }
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inline unsigned char noise_and() { return m_regs[AY_NOISEAND] & 0xff; }
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inline unsigned char noise_or() { return m_regs[AY_NOISEOR] & 0xff; }
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inline bool is_clock_divided() { return ((m_feature & PSG_HAS_INTERNAL_DIVIDER) || ((m_feature & PSG_PIN26_IS_CLKSEL) && (m_flags & YM2149_PIN26_LOW))); }
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// internal helpers
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void set_type(psg_type_t psg_type, bool clk_sel);
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inline float mix_3D();
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void ay8910_write_reg(int r, int v);
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void build_mixer_table();
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// internal state
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psg_type_t m_type;
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int m_streams;
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int m_ready;
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//sound_stream *m_channel;
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bool m_active;
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unsigned char m_register_latch;
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unsigned char m_regs[16 * 2];
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int m_last_enable;
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tone_t m_tone[NUM_CHANNELS];
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envelope_t m_envelope[NUM_CHANNELS];
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unsigned char m_prescale_noise;
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signed short m_noise_value;
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signed short m_count_noise;
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unsigned int m_rng;
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unsigned char m_noise_out;
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unsigned char m_mode;
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unsigned char m_env_step_mask;
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/* init parameters ... */
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int m_step_mul;
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int m_env_step_mul;
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int m_zero_is_off;
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unsigned char m_vol_enabled[NUM_CHANNELS];
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const ay_ym_param *m_par;
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const ay_ym_param *m_par_env;
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short m_vol_table[NUM_CHANNELS][16];
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short m_env_table[NUM_CHANNELS][32];
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short m_vol3d_table[32*32*32*8];
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int m_flags; /* Flags */
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int m_feature; /* Chip specific features */
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int m_res_load[3]; /* Load on channel in ohms */
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};
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class ay8912_device : public ay8910_device
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{
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public:
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ay8912_device(unsigned int clock);
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};
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class ay8913_device : public ay8910_device
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{
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public:
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ay8913_device(unsigned int clock);
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};
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class ay8914_device : public ay8910_device
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{
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public:
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ay8914_device(unsigned int clock);
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/* AY8914 handlers needed due to different register map */
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unsigned char read(int offset);
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void write(int offset, unsigned char data);
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};
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class ay8930_device : public ay8910_device
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{
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public:
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ay8930_device(unsigned int clock, bool clk_sel = false);
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};
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class ym2149_device : public ay8910_device
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{
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public:
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ym2149_device(unsigned int clock, bool clk_sel = false);
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};
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class ym3439_device : public ay8910_device
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{
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public:
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ym3439_device(unsigned int clock, bool clk_sel = false);
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};
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class ymz284_device : public ay8910_device
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{
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public:
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ymz284_device(unsigned int clock);
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};
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class ymz294_device : public ay8910_device
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{
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public:
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ymz294_device(unsigned int clock);
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};
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class sunsoft_5b_sound_device : public ay8910_device
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{
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public:
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sunsoft_5b_sound_device(unsigned int clock);
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};
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#endif // MAME_DEVICES_SOUND_AY8910_H
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