LTVA1
b6ecd79ffa
Merge branch 'master' of https://github.com/tildearrow/furnace into SID3
2024-08-14 21:19:12 +03:00
LTVA1
006fe144ac
version bump...
2024-08-14 21:17:10 +03:00
LTVA1
7c324ec39d
naive channel pair refactor (dumb replace one pair with vector of pairs)
2024-08-14 20:01:16 +03:00
cam900
f906b4ebe4
Safety check for MSM6295 bankswitched address
2024-08-14 17:54:20 +09:00
tildearrow
34517754ad
port TIunA to export framework, part 4
...
index option
2024-08-13 18:42:11 -05:00
tildearrow
249032f096
port TIunA to export framework, part 2
...
progress bars!
2024-08-13 17:47:18 -05:00
tildearrow
bb5ad38fb6
port TIunA to export framework, part 1
...
part 2 includes progress bars and options
2024-08-13 16:50:13 -05:00
tildearrow
aad42210d7
it kinda works
2024-08-13 14:34:06 -05:00
LTVA1
0ea53fdae5
phase reset effects & fix wavetable change
2024-08-13 20:36:45 +03:00
tildearrow
e475b29ec3
a menu
2024-08-13 04:40:26 -05:00
tildearrow
b5e500d85d
dev217
2024-08-13 04:14:46 -05:00
MooingLemur
0224882a42
oops, should have been 47.0.2
2024-08-13 04:11:08 -05:00
MooingLemur
3b9cf70ff5
VERA: bump default chip type
2024-08-13 04:11:08 -05:00
MooingLemur
a8122d3efd
Add VERA 47.0.3 chip type
2024-08-13 04:11:08 -05:00
tildearrow
45eab67fd4
prepare more stuff
2024-08-13 04:10:03 -05:00
LTVA1
46f1ae33c7
add cutoff and pulse width slides for C64, SID2 and SID3
...
Also add clipping for ADSR, duty and cutoff when in instrument types you go SID3 -> SID2 or SID2 -> C64 or SID3 -> C64
2024-08-12 16:54:26 +03:00
LTVA1
e0df55749a
MOAR EFFECTS!!
2024-08-12 12:59:34 +03:00
LTVA1
6417da27e9
add different clock speed, optimize channel processing, add quarter clock speed flag
2024-08-12 11:22:10 +03:00
LTVA1
802f55a26e
hide some settings in inst UI for wave channel, do sample reg writes interleaved with usual reg writes
2024-08-11 21:41:48 +03:00
LTVA1
d38a2b4f37
Merge branch 'tildearrow:master' into SID3
2024-08-11 17:03:06 +03:00
LTVA1
65d65ef81e
add phase invesrion for left/right channel and feedback
2024-08-11 16:47:49 +03:00
tildearrow
8d005f7cbc
fix Linux build
2024-08-10 22:49:22 -05:00
tildearrow
0325f9ed57
NO
2024-08-10 19:50:58 -05:00
tildearrow
148f49eb2b
further preparations
2024-08-10 19:38:50 -05:00
tildearrow
a4aa408912
apvr eatavel eao rso jyrsovrs
...
to-do:
- make an "exporting ROM" dialog with progress and all
- move TIunA export to the ROM export framework
- perhaps do the same with ZSM in the future?
2024-08-10 19:25:01 -05:00
LTVA1
f5877abafe
add distortion to wave channel as well...
2024-08-10 23:45:12 +03:00
LTVA1
845b36e3f2
throw in some shitty asymmetrical distortion (no, it's not 6581 SID distortion you want... sigh)
2024-08-10 22:49:39 +03:00
LTVA1
3206b39525
add filter mode macro, SID2 wave mix macro tips
2024-08-10 14:21:28 +03:00
tildearrow
48523add00
asfgdhk;lj
2024-08-10 02:16:30 -05:00
LTVA1
4ac2338cd7
sigh 6
2024-08-09 15:41:04 +03:00
LTVA1
6349f161eb
sigh 5
2024-08-09 15:13:16 +03:00
LTVA1
37fc2ece2c
fx fix
2024-08-09 14:33:34 +03:00
LTVA1
6bf391b4bc
wavetables and samples for SID3! (unfinished)
2024-08-09 14:30:45 +03:00
tildearrow
a8cd10dd46
DivROMExport: new functions
...
for threading...
2024-08-09 04:27:18 -05:00
tildearrow
d44029647c
TIunA export: possibly optimize
2024-08-09 00:30:16 -05:00
DevEd
d8aa07bbbb
GB: enable VIN input to accomodate multiple chips on hardware
2024-08-08 17:38:10 -05:00
LTVA1
2a322bff4f
implement some basic SID3 effects
...
Wave/PCM chan and pw/cutoff slides coming later ig
2024-08-08 12:11:47 +03:00
tildearrow
69f95722f6
prepare to diagnose TIunA hang
2024-08-07 18:22:36 -05:00
LTVA1
03a6b608be
fix independent noise freq (bad fix), add filter macros
2024-08-06 16:43:24 +03:00
LTVA1
402ff627ae
add flag to disable duty reset on new note for C64/SID2/SID3
2024-08-06 09:00:16 +03:00
LTVA1
bfbc92e1f3
Add LFSR feedback bits, 1-bit noise and wave mix mode macros. I hope I am done with main macros now
2024-08-05 15:50:48 +03:00
LTVA1
2fb518231a
separate noise frequency, almost all main macros, add wavetable size to sysdef, separate wavetable tab
2024-08-05 12:28:22 +03:00
LTVA1
2e321b66c2
proper envelope, phase reset macro, prepare for ad-hoc ADSR params change via macros
2024-08-04 21:28:09 +03:00
LTVA1
986b64bbf0
better phase mod accuracy, optimized panning reg writes
2024-08-04 12:19:33 +03:00
LTVA1
5b92ee0426
sid3: mute, phase mod, panning
2024-08-04 11:32:28 +03:00
LTVA1
f72c4130a9
filter: do not invert signal?
2024-08-04 09:07:19 +03:00
LTVA1
a008707498
Merge branch 'tildearrow:master' into SID3
2024-08-03 06:02:14 +03:00
tildearrow
c2f2aa3024
AY: merge TFX from host12prog
2024-08-02 16:52:54 -05:00
tildearrow
c02556afa7
OPL: don't use fm.rhy
...
issue #2061
2024-08-02 14:32:02 -05:00
LTVA1
e339485131
sigh 4
2024-08-02 19:34:07 +03:00
