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1550 commits

Author SHA1 Message Date
Ian Karlsson 5378974b96 Save the size of each block in a Furnace module 2022-05-27 21:42:14 +02:00
tildearrow 68cc84253c dev99 - major Fractal system change 
7 channels instead of 8 - CSM only supported on ExtCh system
 2022-05-27 05:13:10 -05:00
tildearrow a776129c3d dev98 - YM2612: add Fractal system 
partially done
 2022-05-27 04:02:53 -05:00
tildearrow 0b7d27dc29 YM2612: add reverse sample playback 2022-05-27 02:47:44 -05:00
tildearrow 9d6d84a87f Lynx: sample looping 2022-05-27 01:36:05 -05:00
tildearrow d6282c6949 Lynx: fix PCM mode volume 2022-05-27 01:20:57 -05:00
Waldemar Pawlaszek 65817f7589
Merge branch 'tildearrow:master' into master 2022-05-27 08:11:32 +02:00
Waldemar Pawlaszek 70aa8f7682 Lynx: using DAC output for PCM 2022-05-27 08:10:34 +02:00
tildearrow 1540705b75 WaveSynth: fix it....... again. 2022-05-27 00:35:35 -05:00
tildearrow efaca3b094
Merge pull request #496 from cam900/largecolumns_alt 
Allow more than 64 columns in Dear ImGUI (patched)
 2022-05-27 00:19:21 -05:00
tildearrow 061b312943 SMS: volume table is now non-float 2022-05-26 23:46:42 -05:00
cam900 67a7f39d9a Allow more than 64 columns in Dear ImGUI (patched) 
Improves Channel window displays, with System info.
 2022-05-27 13:38:45 +09:00
tildearrow 905aa1b1a1 SMS: add TI PSG volume table 2022-05-26 23:19:27 -05:00
tildearrow 7e938c869d
Merge pull request #484 from grauw/y8950-adpcm-fix 
More Y8950 ADPCM fixes
 2022-05-26 21:50:51 -05:00
tildearrow 0577aa3569 SMS: early Nuked-PSG modding 2022-05-26 19:00:14 -05:00
tildearrow e3ebe0cb92 SMS: add modified Nuked-PSG core 2022-05-26 18:46:20 -05:00
tildearrow 4874e91bb0 FDS: a bit more 2022-05-26 18:09:46 -05:00
tildearrow 6d441c2ffd FDS: set a post-amp value 2022-05-26 18:07:59 -05:00
tildearrow a52f71ba32 FDS: fix NSFplay core low pass filter precision 
closes #427
 2022-05-26 18:03:57 -05:00
tildearrow 7cf853797a fix .dmf saving 2022-05-26 17:42:30 -05:00
tildearrow 9d36cf5ff0 fix compilation on GCC 12 2022-05-26 13:31:17 -05:00
tildearrow 4b91669e58 Lynx: why did I not commit this 2022-05-26 03:37:34 -05:00
tildearrow 6260bcef54 Lynx: more sample improvements 2022-05-26 00:50:11 -05:00
tildearrow b0c8cfc1f6 Lynx: sample improvements 2022-05-26 00:39:15 -05:00
tildearrow 1811a95e76 Lynx: add sample support! 2022-05-26 00:29:04 -05:00
tildearrow 49a8f77cf1 WaveSynth: fix phase modulation - again 2022-05-25 23:46:07 -05:00
Laurens Holst 4b4bc98417 Stop / reset Y8950 ADPCM before restarting. 
The emulation core treats every write to register 7 with start bit set as
a retrigger. This is not how the real hardware behaves.
 2022-05-26 03:48:49 +02:00
tildearrow 93a4e3d688 WaveSynth: fix phase modulation 
fixes #481
 2022-05-25 00:34:35 -05:00
tildearrow 42a082b2a7 Lynx: add phase reset macro 2022-05-25 00:28:47 -05:00
Laurens Holst a19090ab9b Correct VGM chip ID for Y8950 reset. 2022-05-24 22:08:01 +02:00
tildearrow eb926a668d MSM6258: it works 2022-05-24 00:24:52 -05:00
tildearrow 8ea60f37c5 MSM6258: start work - DO NOT USE! 2022-05-23 19:01:10 -05:00
Laurens Holst fc7b94876d Fix Y8950 ADPCM samples. 
Reverting back to before 70ead337f3, and setting register 8 to 256Kbit RAM mode.
This is what MSX has natively, and allows for the most compact sample storage with
only 4 byte alignment.

Additionally, setting register 8 before writing the start / stop addresses.

Back story:

VGMPlay MSX only supports Y8950 256K DRAM mode and ROM mode (for the latter
it makes sure address writes are shifted). 64K DRAM mode is not supported because
it’s not used by anything and the addresses are specified weirdly with some middle
bits having to be masked out.

The original code in Furnace before the change 70ead337f3 was almost correct except
it needed to set register 8 to 0 to select the 256K DRAM mode. It was set to ROM mode
so the address shift did not match up.

After 70ead337f3 (address shift change) it was also more or less correct except in
“furnacePCM” direct-sample mode the shift was not updated accordingly.

In 1a446c1cdd it selected 64K RAM mode, but for this the addresses need to be specified
differently (see Y8950 manual page 18), and it’s not really the best choice anyway.
 2022-05-24 00:51:13 +02:00
tildearrow f8d851cbc2 the Namco C163 trial 2022-05-23 16:01:35 -05:00
tildearrow 402a1d06cf more chip naming improvements 2022-05-23 15:28:38 -05:00
tildearrow 278979a2f2 change names of 15xx/CUS30 to C15 and C30 2022-05-23 15:08:29 -05:00
tildearrow ff1263aadf ASDFGHJK 2022-05-23 03:43:33 -05:00
tildearrow ced2940336 MSM6295: per-channel osc and muting 2022-05-23 03:18:56 -05:00
tildearrow d3edc58cb1 MSM6295: add clock rate flag 2022-05-23 03:13:22 -05:00
tildearrow 59a722d04a MSM6295: a bit more polishing 2022-05-23 02:56:43 -05:00
tildearrow f25cd17590 early OKI MSM6295 work 2022-05-23 01:46:58 -05:00
tildearrow 133b213998 OPL: new forceIns strategy 2022-05-23 00:18:50 -05:00
tildearrow 519bf244b9 OPL: fix kick volume in drums mode 2022-05-23 00:07:32 -05:00
tildearrow 1a446c1cdd Y8950: let's see 2022-05-22 23:54:33 -05:00
tildearrow 2fa51e482a OPN(A/B/2/B-B): fix absolutely everything 2022-05-22 23:47:41 -05:00
tildearrow 3d4f2cfa13
Merge pull request #453 from grauw/scc-reset-period-counter 
Reset period counter when writing to period registers.
 2022-05-22 22:49:03 -05:00
tildearrow 82eaa45f5d increase range of relative pitch macro 
-32768 to 32767 should be enough
 2022-05-22 22:47:40 -05:00
tildearrow 3aa8ea3625 fix Cxxx/F0xx being delayed in low-latency mode 2022-05-22 22:36:48 -05:00
tildearrow e17c99dcdf allow building Furnace without SDL2 and libsndfile 
for eventual libfurnace
 2022-05-22 19:01:50 -05:00
tildearrow 43981eb59f bring up MSM6295 core 
vgsound_emu by cam900
 2022-05-22 18:06:56 -05:00