From b499878c24754d0f8d0e8462364df0ac3f38eb1e Mon Sep 17 00:00:00 2001 From: tildearrow Date: Wed, 26 May 2021 02:09:18 -0500 Subject: [PATCH] add a define for SN noise start value some SN chips have the start value set to an Atari-like one --- src/engine/platform/sound/sn76496.cpp | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/engine/platform/sound/sn76496.cpp b/src/engine/platform/sound/sn76496.cpp index 2bce97b1b..e0c896b67 100644 --- a/src/engine/platform/sound/sn76496.cpp +++ b/src/engine/platform/sound/sn76496.cpp @@ -144,6 +144,8 @@ #define MAX_OUTPUT 0x7fff +#define NOISE_START 0x8000 +//#define NOISE_START 0x0f35 sn76496_base_device::sn76496_base_device( const char *tag, @@ -193,7 +195,7 @@ void sn76496_base_device::device_start() m_count[i] = 0; } - m_RNG = m_feedback_mask; + m_RNG = NOISE_START; m_output[3] = m_RNG & 1; m_current_clock = m_clock_divider-1; @@ -230,7 +232,7 @@ void sn76496_base_device::write(u8 data) { r = (data & 0x70) >> 4; m_last_register = r; - if (((m_ncr_style_psg) && (r == 6)) && ((data&0x04) != (m_register[6]&0x04))) m_RNG = m_feedback_mask; // NCR-style PSG resets the LFSR only on a mode write which actually changes the state of bit 2 of register 6 + if (((m_ncr_style_psg) && (r == 6)) && ((data&0x04) != (m_register[6]&0x04))) m_RNG = NOISE_START; // NCR-style PSG resets the LFSR only on a mode write which actually changes the state of bit 2 of register 6 m_register[r] = (m_register[r] & 0x3f0) | (data & 0x0f); } else @@ -269,7 +271,7 @@ void sn76496_base_device::write(u8 data) n = m_register[6]; // N/512,N/1024,N/2048,Tone #3 output m_period[3] = ((n&3) == 3)? (m_period[2]<<1) : (1 << (5+(n&3))); - if (!(m_ncr_style_psg)) m_RNG = m_feedback_mask; + if (!(m_ncr_style_psg)) m_RNG = NOISE_START; } break; }