implement KVS on the rest of FM chips
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89916de067
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b053d31a6d
13 changed files with 71 additions and 65 deletions
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@ -26,6 +26,8 @@
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#define rWrite(a,v) if (!skipRegisterWrites) {pendingWrites[a]=v;}
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#define immWrite(a,v) if (!skipRegisterWrites) {writes.emplace(a,v); if (dumpWrites) {addWrite(a,v);} }
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#define KVSL(x,y) ((chan[x].state.op[orderedOpsL1[ops==4][y]].kvs==2 && isOutputL[ops==4][chan[x].state.alg][y]) || chan[x].state.op[orderedOpsL1[ops==4][y]].kvs==1)
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#define CHIP_FREQBASE chipFreqBase
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// N = invalid
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@ -138,6 +140,11 @@ const bool isOutputL[2][4][4]={
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#undef N
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const int orderedOpsL1[2][4]={
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{0, 1, 0, 1}, // 2-op
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{0, 2, 1, 3} // 4-op
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};
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const int orderedOpsL[4]={
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0,2,1,3
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};
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@ -288,7 +295,7 @@ void DivPlatformOPL::tick(bool sysTick) {
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if (isMuted[i]) {
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rWrite(baseAddr+ADDR_KSL_TL,63|(op.ksl<<6));
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} else {
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if (isOutputL[ops==4][chan[i].state.alg][j] || i>melodicChans) {
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if (KVSL(i,j) || i>melodicChans) {
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rWrite(baseAddr+ADDR_KSL_TL,(63-VOL_SCALE_LOG(63-op.tl,chan[i].outVol&0x3f,63))|(op.ksl<<6));
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} else {
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rWrite(baseAddr+ADDR_KSL_TL,op.tl|(op.ksl<<6));
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@ -406,7 +413,7 @@ void DivPlatformOPL::tick(bool sysTick) {
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if (isMuted[i]) {
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rWrite(baseAddr+ADDR_KSL_TL,63|(op.ksl<<6));
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} else {
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if (isOutputL[ops==4][chan[i].state.alg][j] || i>melodicChans) {
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if (KVSL(i,j) || i>melodicChans) {
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rWrite(baseAddr+ADDR_KSL_TL,(63-VOL_SCALE_LOG(63-op.tl,chan[i].outVol&0x3f,63))|(op.ksl<<6));
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} else {
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rWrite(baseAddr+ADDR_KSL_TL,op.tl|(op.ksl<<6));
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@ -610,7 +617,7 @@ void DivPlatformOPL::muteChannel(int ch, bool mute) {
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if (isMuted[ch]) {
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rWrite(baseAddr+ADDR_KSL_TL,63|(op.ksl<<6));
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} else {
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if (isOutputL[ops==4][chan[ch].state.alg][i] || ch>melodicChans) {
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if (KVSL(ch,i) || ch>melodicChans) {
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rWrite(baseAddr+ADDR_KSL_TL,(63-VOL_SCALE_LOG(63-op.tl,chan[ch].outVol&0x3f,63))|(op.ksl<<6));
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} else {
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rWrite(baseAddr+ADDR_KSL_TL,op.tl|(op.ksl<<6));
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@ -783,7 +790,7 @@ int DivPlatformOPL::dispatch(DivCommand c) {
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if (isMuted[c.chan]) {
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rWrite(baseAddr+ADDR_KSL_TL,63|(op.ksl<<6));
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} else {
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if (isOutputL[ops==4][chan[c.chan].state.alg][i] || c.chan>melodicChans) {
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if (KVSL(c.chan,i) || c.chan>melodicChans) {
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rWrite(baseAddr+ADDR_KSL_TL,(63-VOL_SCALE_LOG(63-op.tl,chan[c.chan].outVol&0x3f,63))|(op.ksl<<6));
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} else {
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rWrite(baseAddr+ADDR_KSL_TL,op.tl|(op.ksl<<6));
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@ -899,7 +906,7 @@ int DivPlatformOPL::dispatch(DivCommand c) {
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if (isMuted[c.chan]) {
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rWrite(baseAddr+ADDR_KSL_TL,63|(op.ksl<<6));
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} else {
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if (isOutputL[ops==4][chan[c.chan].state.alg][i] || c.chan>melodicChans) {
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if (KVSL(c.chan,i) || c.chan>melodicChans) {
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rWrite(baseAddr+ADDR_KSL_TL,(63-VOL_SCALE_LOG(63-op.tl,chan[c.chan].outVol&0x3f,63))|(op.ksl<<6));
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} else {
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rWrite(baseAddr+ADDR_KSL_TL,op.tl|(op.ksl<<6));
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@ -1048,7 +1055,7 @@ int DivPlatformOPL::dispatch(DivCommand c) {
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if (isMuted[c.chan]) {
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rWrite(baseAddr+ADDR_KSL_TL,63|(op.ksl<<6));
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} else {
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if (isOutputL[ops==4][chan[c.chan].state.alg][c.value] || c.chan>melodicChans) {
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if (KVSL(c.chan,c.value) || c.chan>melodicChans) {
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rWrite(baseAddr+ADDR_KSL_TL,(63-VOL_SCALE_LOG(63-op.tl,chan[c.chan].outVol&0x3f,63))|(op.ksl<<6));
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} else {
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rWrite(baseAddr+ADDR_KSL_TL,op.tl|(op.ksl<<6));
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@ -1278,7 +1285,7 @@ int DivPlatformOPL::dispatch(DivCommand c) {
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if (isMuted[c.chan]) {
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rWrite(baseAddr+ADDR_KSL_TL,63|(op.ksl<<6));
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} else {
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if (isOutputL[ops==4][chan[c.chan].state.alg][i] || c.chan>melodicChans) {
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if (KVSL(c.chan,i) || c.chan>melodicChans) {
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rWrite(baseAddr+ADDR_KSL_TL,(63-VOL_SCALE_LOG(63-op.tl,chan[c.chan].outVol&0x3f,63))|(op.ksl<<6));
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} else {
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rWrite(baseAddr+ADDR_KSL_TL,op.tl|(op.ksl<<6));
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@ -1295,7 +1302,7 @@ int DivPlatformOPL::dispatch(DivCommand c) {
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if (isMuted[c.chan]) {
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rWrite(baseAddr+ADDR_KSL_TL,63|(op.ksl<<6));
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} else {
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if (isOutputL[ops==4][chan[c.chan].state.alg][c.value] || c.chan>melodicChans) {
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if (KVSL(c.chan,c.value) || c.chan>melodicChans) {
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rWrite(baseAddr+ADDR_KSL_TL,(63-VOL_SCALE_LOG(63-op.tl,chan[c.chan].outVol&0x3f,63))|(op.ksl<<6));
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} else {
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rWrite(baseAddr+ADDR_KSL_TL,op.tl|(op.ksl<<6));
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@ -1372,7 +1379,7 @@ void DivPlatformOPL::forceIns() {
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if (isMuted[i]) {
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rWrite(baseAddr+ADDR_KSL_TL,63|(op.ksl<<6));
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} else {
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if (isOutputL[ops==4][chan[i].state.alg][j] || i>melodicChans) {
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if (KVSL(i,j) || i>melodicChans) {
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rWrite(baseAddr+ADDR_KSL_TL,(63-VOL_SCALE_LOG(63-op.tl,chan[i].outVol&0x3f,63))|(op.ksl<<6));
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} else {
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rWrite(baseAddr+ADDR_KSL_TL,op.tl|(op.ksl<<6));
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