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Revert "update YM268-LLE"

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This reverts commit e4ffb2b3d3.
This commit is contained in:
tildearrow 2025-04-13 15:38:43 -05:00
parent 036e33b730
commit a3b77edbba
3 changed files with 12 additions and 16 deletions
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6
extern/YM2608-LLE/README.md vendored
View file

@ -1,11 +1,9 @@
# YM2608-LLE # YM2608-LLE
Very low-level Yamaha YM2608B(OPNA), YM2610/YM2610B(OPNB) and YM2612 (OPN2) emulator using die shots. Very low-level Yamaha YM2608B(OPNA), YM2610(OPNB) and YM2612 (OPN2) emulator using die shots.
Special thanks to @ika-musume for decapping YM2608B, John McMaster for decapping YM2610, HardWareMan for decapping YM2612, and furrtek for decapping YM2610B.. Special thanks to @ika-musume for decapping YM2608B, John McMaster for decapping YM2610, and HardWareMan for decapping YM2612.
https://siliconpr0n.org/map/yamaha/ym2610/ https://siliconpr0n.org/map/yamaha/ym2610/
http://nemesis.hacking-cult.org/MegaDrive/Documentation/YM2612/YM2612_Stiched.jpg http://nemesis.hacking-cult.org/MegaDrive/Documentation/YM2612/YM2612_Stiched.jpg
https://siliconpr0n.org/map/yamaha/ym2610b/

21
extern/YM2608-LLE/fmopna_impl.c vendored
View file

@ -466,6 +466,8 @@ void FMOPNA_2612_Clock(fmopna_2612_t* chip, int clk)
chip->reg_timer_b_load[0] = 0; chip->reg_timer_b_load[0] = 0;
chip->reg_timer_a_enable[0] = 0; chip->reg_timer_a_enable[0] = 0;
chip->reg_timer_b_enable[0] = 0; chip->reg_timer_b_enable[0] = 0;
chip->reg_timer_a_reset[0] = 0;
chip->reg_timer_b_reset[0] = 0;
chip->reg_kon_operator[0] = 0; chip->reg_kon_operator[0] = 0;
chip->reg_kon_channel[0] = 0; chip->reg_kon_channel[0] = 0;
#ifdef FMOPNA_YM2608 #ifdef FMOPNA_YM2608
@ -571,6 +573,8 @@ void FMOPNA_2612_Clock(fmopna_2612_t* chip, int clk)
chip->reg_timer_b_load[0] = (chip->data_bus1 >> 1) & 1; chip->reg_timer_b_load[0] = (chip->data_bus1 >> 1) & 1;
chip->reg_timer_a_enable[0] = (chip->data_bus1 >> 2) & 1; chip->reg_timer_a_enable[0] = (chip->data_bus1 >> 2) & 1;
chip->reg_timer_b_enable[0] = (chip->data_bus1 >> 3) & 1; chip->reg_timer_b_enable[0] = (chip->data_bus1 >> 3) & 1;
chip->reg_timer_a_reset[0] = (chip->data_bus1 >> 4) & 1;
chip->reg_timer_b_reset[0] = (chip->data_bus1 >> 5) & 1;
} }
else else
{ {
@ -579,6 +583,8 @@ void FMOPNA_2612_Clock(fmopna_2612_t* chip, int clk)
chip->reg_timer_b_load[0] = chip->reg_timer_b_load[1]; chip->reg_timer_b_load[0] = chip->reg_timer_b_load[1];
chip->reg_timer_a_enable[0] = chip->reg_timer_a_enable[1]; chip->reg_timer_a_enable[0] = chip->reg_timer_a_enable[1];
chip->reg_timer_b_enable[0] = chip->reg_timer_b_enable[1]; chip->reg_timer_b_enable[0] = chip->reg_timer_b_enable[1];
chip->reg_timer_a_reset[0] = 0;
chip->reg_timer_b_reset[0] = 0;
} }
if (chip->addr_28[1] && (chip->data_bus1 & 0x100) == 0 && chip->write1_en) if (chip->addr_28[1] && (chip->data_bus1 & 0x100) == 0 && chip->write1_en)
{ {
@ -630,9 +636,6 @@ void FMOPNA_2612_Clock(fmopna_2612_t* chip, int clk)
#endif #endif
} }
chip->reg_timer_a_reset[0] = chip->addr_27[1] && (chip->data_bus1 & 0x100) == 0 && chip->write1_en && ((chip->data_bus1 >> 4) & 1) != 0;
chip->reg_timer_b_reset[0] = chip->addr_27[1] && (chip->data_bus1 & 0x100) == 0 && chip->write1_en && ((chip->data_bus1 >> 5) & 1) != 0;
int rst1 = chip->reg_cnt_sync || chip->ic; int rst1 = chip->reg_cnt_sync || chip->ic;
int of = (chip->reg_cnt1[1] & 2) != 0; int of = (chip->reg_cnt1[1] & 2) != 0;
@ -937,7 +940,7 @@ void FMOPNA_2612_Clock(fmopna_2612_t* chip, int clk)
) )
#ifdef FMOPNA_YM2610 #ifdef FMOPNA_YM2610
// tildearrow: changed to allow YM2610B emulation // tildearrow: changed to allow YM2610B emulation
&& (chip->ym2610b || (chip->reg_kon_channel[0] & 3) != 0) || chip->input.ym2610b) && (chip->ym2610b || (chip->reg_kon_channel[0] & 3) != 0)
#endif #endif
; ;
@ -1330,7 +1333,7 @@ void FMOPNA_2612_Clock(fmopna_2612_t* chip, int clk)
chip->pg_add[4] = chip->pg_add[3]; chip->pg_add[4] = chip->pg_add[3];
chip->pg_reset[1] = chip->pg_reset[0]; chip->pg_reset[1] = chip->pg_reset[0];
chip->pg_reset[3] = chip->pg_reset[2] || (chip->reg_test_21[1] & 8) != 0; chip->pg_reset[3] = chip->pg_reset[2];
memcpy(&chip->pg_phase[0][1], &chip->pg_phase[1][0], 22 * sizeof(int)); memcpy(&chip->pg_phase[0][1], &chip->pg_phase[1][0], 22 * sizeof(int));
@ -2253,8 +2256,8 @@ void FMOPNA_2612_Clock(fmopna_2612_t* chip, int clk)
break; break;
#ifdef FMOPNA_YM2608 #ifdef FMOPNA_YM2608
case 0xe: case 0xe:
chip->data_bus1 &= ~255; chip->data_bus1 &= ~15;
chip->data_bus1 |= chip->input.gpio_a & 255; chip->data_bus1 |= chip->input.gpio_a & 15;
break; break;
case 0xf: case 0xf:
chip->data_bus1 &= ~255; chip->data_bus1 &= ~255;
@ -2433,10 +2436,6 @@ void FMOPNA_2612_Clock(fmopna_2612_t* chip, int clk)
chip->o_analog += chip->o_analog_ch[0] = volume_lut[sign_a ? 0 : vol_a]; chip->o_analog += chip->o_analog_ch[0] = volume_lut[sign_a ? 0 : vol_a];
chip->o_analog += chip->o_analog_ch[1] = volume_lut[sign_b ? 0 : vol_b]; chip->o_analog += chip->o_analog_ch[1] = volume_lut[sign_b ? 0 : vol_b];
chip->o_analog += chip->o_analog_ch[2] = volume_lut[sign_c ? 0 : vol_c]; chip->o_analog += chip->o_analog_ch[2] = volume_lut[sign_c ? 0 : vol_c];
//please work
chip->o_gpio_a_d = (chip->ssg_mode & 64) == 0;
chip->o_gpio_b_d = (chip->ssg_mode & 128) == 0;
} }
{ {

1
extern/YM2608-LLE/fmopna_impl.h vendored
View file

@ -52,7 +52,6 @@ typedef struct {
#ifdef FMOPNA_YM2610 #ifdef FMOPNA_YM2610
int rad; int rad;
int pad; int pad;
int ym2610b;
#endif #endif
} }
#ifdef FMOPNA_YM2608 #ifdef FMOPNA_YM2608