diff --git a/doc/7-systems/msm6295.md b/doc/7-systems/msm6295.md
index 3785cc62f..12900b081 100644
--- a/doc/7-systems/msm6295.md
+++ b/doc/7-systems/msm6295.md
@@ -5,3 +5,26 @@ an upgrade from 6258 - it provides 4 ADPCM channels, at max 32 KHz (still no var
 # effects
 
 - `20xx`: **set chip output rate.**
+# config flags
+## chip clock rates
+like msm6258, msm6295 is an extremely basic ADPCM sound codec. it has no variable frequency rate, it depends on clock rate of a chip itself. furnace supports following rates:
+
+- 1 MHz, resulting sample rate is 7576 Hz
+- 1.056 MHz, resulting sample rate is 8000 Hz
+- 1.02 MHz, resulting sample rate is 7727 Hz
+- 1.193 MHz, resulting sample rate is 9038 Hz
+- 0.89 MHz, resulting sample rate is 6742 Hz
+- 0.875 MHz, resulting sample rate is 6629 Hz
+- 0.9375 MHz  resulting sample rate is 7102 Hz
+- 1.5 MHz, resulting sample rate is 11364 Hz
+- 1.79 MHz, resulting sample rate is 13561 Hz
+- 2 MHz, resulting sample rate is 15152 Hz 
+- 2.112 MHz, resulting sample rate is 16000 Hz
+- 3 MHz, resulting sample rate is 22728 Hz
+- 3.58 MHz, resulting sample rate is 27122 Hz
+- 4 MHz, resulting sample rate is 30304 Hz
+- 4.224 MHz resulting sample rate is 32000 Hz
+
+  ## chip clock divisor
+
+MSM6295 clock rate could be divided by 132 (resulting sample rates above), or by 165. To get a clock rte using divisor of 165, formula is clock rate (in Hz) / 165. Example: 1 MHz MSM6295 in 165 divisor mode results in output rate of 6060 Hz.