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ZSM export: fix two bugs w/ looped sample export

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This commit is contained in:
MooingLemur 2023-07-08 23:51:54 -07:00 • committed by tildearrow
parent e600747152
commit 73ea490fdb
2 changed files with 10 additions and 5 deletions
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9
src/engine/platform/vera.cpp
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@ -236,9 +236,12 @@ void DivPlatformVERA::tick(bool sysTick) {
if (s->samples>0) {
if (s->isLoopable()) {
// Inform the export process of the loop point for this sample
addWrite(67,s->loopStart&0xff);
addWrite(67,(s->loopStart>>8)&0xff);
addWrite(67,(s->loopStart>>16)&0xff);
int tmp_ls=(s->loopStart<<1); // for stereo
if (chan[16].pcm.depth16)
tmp_ls<<=1; // for 16 bit
addWrite(67,tmp_ls&0xff);
addWrite(67,(tmp_ls>>8)&0xff);
addWrite(67,(tmp_ls>>16)&0xff);
}
while (true) {
short tmp_l=0;