get it done

OPL UNFINISHED

src/engine/platform/arcade.cpp

@@ -55,10 +55,14 @@ void DivPlatformArcade::acquire_nuked(short** buf, size_t len) {
   thread_local int o[2];
 
   for (size_t h=0; h<len; h++) {
+    if (delay>0) delay--;
     for (int i=0; i<8; i++) {
-      if (!writes.empty() && !fm.write_busy) {
+      if (delay<=0 && !writes.empty() && !fm.write_busy) {
         QueuedWrite& w=writes.front();
-        if (w.addrOrVal) {
+        if (w.addr==0xfffffffe) {
+          delay=w.val;
+          writes.pop_front();
+        } else if (w.addrOrVal) {
           OPM_Write(&fm,1,w.val);
           regPool[w.addr&0xff]=w.val;
           //printf("write: %x = %.2x\n",w.addr,w.val);
@@ -101,11 +105,15 @@ void DivPlatformArcade::acquire_ymfm(short** buf, size_t len) {
     if (!writes.empty()) {
       if (--delay<1) {
         QueuedWrite& w=writes.front();
-        fm_ymfm->write(0x0+((w.addr>>8)<<1),w.addr);
+        if (w.addr==0xfffffffe) {
-        fm_ymfm->write(0x1+((w.addr>>8)<<1),w.val);
+          delay=w.val;
-        regPool[w.addr&0xff]=w.val;
+        } else {
+          fm_ymfm->write(0x0+((w.addr>>8)<<1),w.addr);
+          fm_ymfm->write(0x1+((w.addr>>8)<<1),w.val);
+          regPool[w.addr&0xff]=w.val;
+          delay=1;
+        }
         writes.pop_front();
-        delay=1;
       }
     }
 
@@ -380,9 +388,7 @@ void DivPlatformArcade::tick(bool sysTick) {
 
   // hard reset handling
   if (mustHardReset) {
-    for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
+    immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
-      immWrite(0x1f,i&0xff);
-    }
     for (int i=0; i<8; i++) {
       if ((chan[i].keyOn || chan[i].opMaskChanged) && chan[i].hardReset) {
         // restore SL/RR

src/engine/platform/genesisext.cpp

@@ -693,9 +693,7 @@ void DivPlatformGenesisExt::tick(bool sysTick) {
 
     // hard reset handling
     if (mustHardReset) {
-      for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
+      immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
-        immWrite(0xf0,i&0xff);
-      }
       for (int i=0; i<4; i++) {
         if (opChan[i].keyOn && opChan[i].hardReset) {
           // restore SL/RR

src/engine/platform/opl.cpp

@@ -190,33 +190,37 @@ void DivPlatformOPL::acquire_nuked(short** buf, size_t len) {
   for (size_t h=0; h<len; h++) {
     os[0]=0; os[1]=0; os[2]=0; os[3]=0; os[4]=0; os[5]=0;
     if (!writes.empty() && --delay<0) {
-      delay=1;
       QueuedWrite& w=writes.front();
-      if (w.addr>=0x200) {
+      if (w.addr==0xfffffffe) {
-        pcm.writeReg(w.addr&0xff,w.val);
+        delay=w.val;
-        regPool[0x200|(w.addr&0xff)]=w.val;
       } else {
-        switch (w.addr) {
+        delay=1;
-          case 8:
+        if (w.addr>=0x200) {
-            if (adpcmChan>=0) {
+          pcm.writeReg(w.addr&0xff,w.val);
-              adpcmB->write(w.addr-7,(w.val&15)|0x80);
+          regPool[0x200|(w.addr&0xff)]=w.val;
-              OPL3_WriteReg(&fm,w.addr,w.val&0xc0);
+        } else {
-            } else {
+          switch (w.addr) {
+            case 8:
+              if (adpcmChan>=0) {
+                adpcmB->write(w.addr-7,(w.val&15)|0x80);
+                OPL3_WriteReg(&fm,w.addr,w.val&0xc0);
+              } else {
+                OPL3_WriteReg(&fm,w.addr,w.val);
+              }
+              break;
+            case 7: case 9: case 10: case 11: case 12: case 13: case 14: case 15: case 16: case 17: case 18: case 21: case 22: case 23:
+              if (adpcmChan>=0) {
+                adpcmB->write(w.addr-7,w.val);
+              } else {
+                OPL3_WriteReg(&fm,w.addr,w.val);
+              }
+              break;
+            default:
               OPL3_WriteReg(&fm,w.addr,w.val);
-            }
+              break;
-            break;
+          }
-          case 7: case 9: case 10: case 11: case 12: case 13: case 14: case 15: case 16: case 17: case 18: case 21: case 22: case 23:
+          regPool[w.addr&511]=w.val;
-            if (adpcmChan>=0) {
-              adpcmB->write(w.addr-7,w.val);
-            } else {
-              OPL3_WriteReg(&fm,w.addr,w.val);
-            }
-            break;
-          default:
-            OPL3_WriteReg(&fm,w.addr,w.val);
-            break;
         }
-        regPool[w.addr&511]=w.val;
       }
       writes.pop();
     }
@@ -353,11 +357,11 @@ void DivPlatformOPL::acquire_ymfm1(short** buf, size_t len) {
 
   for (size_t h=0; h<len; h++) {
     if (!writes.empty() && --delay<0) {
-      delay=1;
       QueuedWrite& w=writes.front();
 
       fm_ymfm1->write(0,w.addr);
       fm_ymfm1->write(1,w.val);
+      delay=1;
 
       regPool[w.addr&511]=w.val;
       writes.pop();
@@ -395,11 +399,11 @@ void DivPlatformOPL::acquire_ymfm2(short** buf, size_t len) {
 
   for (size_t h=0; h<len; h++) {
     if (!writes.empty() && --delay<0) {
-      delay=1;
       QueuedWrite& w=writes.front();
 
       fm_ymfm2->write(0,w.addr);
       fm_ymfm2->write(1,w.val);
+      delay=1;
 
       regPool[w.addr&511]=w.val;
       writes.pop();
@@ -438,11 +442,11 @@ void DivPlatformOPL::acquire_ymfm8950(short** buf, size_t len) {
 
   for (size_t h=0; h<len; h++) {
     if (!writes.empty() && --delay<0) {
-      delay=1;
       QueuedWrite& w=writes.front();
 
       fm_ymfm8950->write(0,w.addr);
       fm_ymfm8950->write(1,w.val);
+      delay=1;
 
       regPool[w.addr&511]=w.val;
       writes.pop();
@@ -482,11 +486,11 @@ void DivPlatformOPL::acquire_ymfm3(short** buf, size_t len) {
 
   for (size_t h=0; h<len; h++) {
     if (!writes.empty() && --delay<0) {
-      delay=1;
       QueuedWrite& w=writes.front();
 
       fm_ymfm3->write((w.addr&0x100)?2:0,w.addr);
       fm_ymfm3->write(1,w.val);
+      delay=1;
 
       regPool[w.addr&511]=w.val;
       writes.pop();
@@ -582,11 +586,11 @@ void DivPlatformOPL::acquire_ymfm4(short** buf, size_t len) {
 
   for (size_t h=0; h<len; h++) {
     if (!writes.empty() && --delay<0) {
-      delay=1;
       QueuedWrite& w=writes.front();
 
       fm_ymfm4->write((w.addr&0x200)?4:(w.addr&0x100)?2:0,w.addr);
       fm_ymfm4->write((w.addr&0x200)?5:1,w.val);
+      delay=1;
 
       regPool[(w.addr&0x200)?(0x200+(w.addr&255)):(w.addr&511)]=w.val;
       writes.pop();
@@ -1480,9 +1484,7 @@ void DivPlatformOPL::tick(bool sysTick) {
 
   // hard reset handling
   if (mustHardReset) {
-    for (unsigned int i=hardResetElapsed; i<128; i++) {
+    immWrite(0xfffffffe,128-hardResetElapsed);
-      immWrite(0x3f,i&0xff);
-    }
     for (int i=0x80; i<0xa0; i++) {
       if (weWillWriteRRLater[i-0x80]) {
         immWrite(i,pendingWrites[i]&0xff);

src/engine/platform/opl.h

@@ -98,11 +98,11 @@ class DivPlatformOPL: public DivDispatch {
     DivDispatchOscBuffer* oscBuf[44];
     bool isMuted[44];
     struct QueuedWrite {
-      unsigned short addr;
+      unsigned int addr;
       unsigned char val;
       bool addrOrVal;
       QueuedWrite(): addr(0), val(0), addrOrVal(false) {}
-      QueuedWrite(unsigned short a, unsigned char v): addr(a), val(v), addrOrVal(false) {}
+      QueuedWrite(unsigned int a, unsigned char v): addr(a), val(v), addrOrVal(false) {}
     };
     FixedQueue<QueuedWrite,4096> writes;
 

src/engine/platform/tx81z.cpp

@@ -67,11 +67,15 @@ void DivPlatformTX81Z::acquire(short** buf, size_t len) {
     if (!writes.empty()) {
       if (--delay<1) {
         QueuedWrite& w=writes.front();
-        fm_ymfm->write(0x0+((w.addr>>8)<<1),w.addr);
+        if (w.addr==0xfffffffe) {
-        fm_ymfm->write(0x1+((w.addr>>8)<<1),w.val);
+          delay=w.val;
-        regPool[w.addr&0xff]=w.val;
+        } else {
+          fm_ymfm->write(0x0+((w.addr>>8)<<1),w.addr);
+          fm_ymfm->write(0x1+((w.addr>>8)<<1),w.val);
+          regPool[w.addr&0xff]=w.val;
+          delay=1;
+        }
         writes.pop_front();
-        delay=1;
       }
     }
     
@@ -419,9 +423,7 @@ void DivPlatformTX81Z::tick(bool sysTick) {
 
   // hard reset handling
   if (mustHardReset) {
-    for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
+    immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
-      immWrite(0x1f,i&0xff);
-    }
     for (int i=0; i<8; i++) {
       if (chan[i].keyOn && chan[i].hardReset) {
         // restore SL/RR

src/engine/platform/ym2203.cpp

@@ -187,7 +187,10 @@ void DivPlatformYM2203::acquire_combo(short** buf, size_t len) {
         if (--delay<1 && !(fm->read(0)&0x80)) {
           QueuedWrite& w=writes.front();
 
-          if (w.addr<=0x1c || w.addr==0x2d || w.addr==0x2e || w.addr==0x2f) {
+          if (w.addr==0xfffffffe) {
+            delay=w.val;
+            writes.pop_front();
+          } else if (w.addr<=0x1c || w.addr==0x2d || w.addr==0x2e || w.addr==0x2f) {
             // ymfm write
             fm->write(0x0,w.addr);
             fm->write(0x1,w.val);
@@ -267,11 +270,15 @@ void DivPlatformYM2203::acquire_ymfm(short** buf, size_t len) {
     if (!writes.empty()) {
       if (--delay<1) {
         QueuedWrite& w=writes.front();
-        fm->write(0x0,w.addr);
+        if (w.addr==0xfffffffe) {
-        fm->write(0x1,w.val);
+          delay=w.val*6;
-        regPool[w.addr&0xff]=w.val;
+        } else {
+          fm->write(0x0,w.addr);
+          fm->write(0x1,w.val);
+          regPool[w.addr&0xff]=w.val;
+          delay=6;
+        }
         writes.pop_front();
-        delay=6;
       }
     }
     
@@ -661,9 +668,7 @@ void DivPlatformYM2203::tick(bool sysTick) {
 
   // hard reset handling
   if (mustHardReset) {
-    for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
+    immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
-      immWrite(0xf0,i&0xff);
-    }
     for (int i=0; i<3; i++) {
       if (i==2 && extMode) continue;
       if ((chan[i].keyOn || chan[i].opMaskChanged) && chan[i].hardReset) {

src/engine/platform/ym2203ext.cpp

@@ -595,9 +595,7 @@ void DivPlatformYM2203Ext::tick(bool sysTick) {
 
     // hard reset handling
     if (mustHardReset) {
-      for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
+      immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
-        immWrite(0xf0,i&0xff);
-      }
       for (int i=0; i<4; i++) {
         if (opChan[i].keyOn && opChan[i].hardReset) {
           // restore SL/RR

src/engine/platform/ym2608.cpp

@@ -338,7 +338,10 @@ void DivPlatformYM2608::acquire_combo(short** buf, size_t len) {
         if (--delay<1 && !(fm->read(0)&0x80)) {
           QueuedWrite& w=writes.front();
 
-          if (w.addr<=0x1d || w.addr==0x2d || w.addr==0x2e || w.addr==0x2f || (w.addr>=0x100 && w.addr<=0x12d)) {
+          if (w.addr==0xfffffffe) {
+            delay=w.val;
+            writes.pop_front();
+          } else if (w.addr<=0x1d || w.addr==0x2d || w.addr==0x2e || w.addr==0x2f || (w.addr>=0x100 && w.addr<=0x12d)) {
             // ymfm write
             fm->write(0x0+((w.addr>>8)<<1),w.addr);
             fm->write(0x1+((w.addr>>8)<<1),w.val);
@@ -451,11 +454,15 @@ void DivPlatformYM2608::acquire_ymfm(short** buf, size_t len) {
     if (!writes.empty()) {
       if (--delay<1) {
         QueuedWrite& w=writes.front();
-        fm->write(0x0+((w.addr>>8)<<1),w.addr);
+        if (w.addr==0xfffffffe) {
-        fm->write(0x1+((w.addr>>8)<<1),w.val);
+          delay=w.val*4;
-        regPool[w.addr&0x1ff]=w.val;
+        } else {
+          fm->write(0x0+((w.addr>>8)<<1),w.addr);
+          fm->write(0x1+((w.addr>>8)<<1),w.val);
+          regPool[w.addr&0x1ff]=w.val;
+          delay=4;
+        }
         writes.pop_front();
-        delay=4;
       }
     }
     
@@ -1028,9 +1035,7 @@ void DivPlatformYM2608::tick(bool sysTick) {
 
   // hard reset handling
   if (mustHardReset) {
-    for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
+    immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
-      immWrite(0xf0,i&0xff);
-    }
     for (int i=0; i<6; i++) {
       if (i==2 && extMode) continue;
       if ((chan[i].keyOn || chan[i].opMaskChanged) && chan[i].hardReset) {

src/engine/platform/ym2608ext.cpp

@@ -646,9 +646,7 @@ void DivPlatformYM2608Ext::tick(bool sysTick) {
 
     // hard reset handling
     if (mustHardReset) {
-      for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
+      immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
-        immWrite(0xf0,i&0xff);
-      }
       for (int i=0; i<4; i++) {
         if (opChan[i].keyOn && opChan[i].hardReset) {
           // restore SL/RR

src/engine/platform/ym2610.cpp

@@ -274,7 +274,10 @@ void DivPlatformYM2610::acquire_combo(short** buf, size_t len) {
         if (--delay<1 && !(fm->read(0)&0x80)) {
           QueuedWrite& w=writes.front();
 
-          if (w.addr<=0x1c || (w.addr>=0x100 && w.addr<=0x12d)) {
+          if (w.addr==0xfffffffe) {
+            delay=w.val;
+            writes.pop_front();
+          } else if (w.addr<=0x1c || (w.addr>=0x100 && w.addr<=0x12d)) {
             // ymfm write
             fm->write(0x0+((w.addr>>8)<<1),w.addr);
             fm->write(0x1+((w.addr>>8)<<1),w.val);
@@ -385,11 +388,15 @@ void DivPlatformYM2610::acquire_ymfm(short** buf, size_t len) {
     if (!writes.empty()) {
       if (--delay<1 && !(fm->read(0)&0x80)) {
         QueuedWrite& w=writes.front();
-        fm->write(0x0+((w.addr>>8)<<1),w.addr);
+        if (w.addr==0xfffffffe) {
-        fm->write(0x1+((w.addr>>8)<<1),w.val);
+          delay=w.val;
-        regPool[w.addr&0x1ff]=w.val;
+        } else {
+          fm->write(0x0+((w.addr>>8)<<1),w.addr);
+          fm->write(0x1+((w.addr>>8)<<1),w.val);
+          regPool[w.addr&0x1ff]=w.val;
+          delay=1;
+        }
         writes.pop_front();
-        delay=1;
       }
     }
     
@@ -956,9 +963,7 @@ void DivPlatformYM2610::tick(bool sysTick) {
 
   // hard reset handling
   if (mustHardReset) {
-    for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
+    immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
-      immWrite(0xf0,i&0xff);
-    }
     for (int i=0; i<(psgChanOffs-isCSM); i++) {
       if (i==1 && extMode) continue;
       if ((chan[i].keyOn || chan[i].opMaskChanged) && chan[i].hardReset) {

src/engine/platform/ym2610b.cpp

@@ -338,7 +338,10 @@ void DivPlatformYM2610B::acquire_combo(short** buf, size_t len) {
         if (--delay<1 && !(fm->read(0)&0x80)) {
           QueuedWrite& w=writes.front();
 
-          if (w.addr<=0x1c || (w.addr>=0x100 && w.addr<=0x12d)) {
+          if (w.addr==0xfffffffe) {
+            delay=w.val;
+            writes.pop_front();
+          } else if (w.addr<=0x1c || (w.addr>=0x100 && w.addr<=0x12d)) {
             // ymfm write
             fm->write(0x0+((w.addr>>8)<<1),w.addr);
             fm->write(0x1+((w.addr>>8)<<1),w.val);
@@ -451,11 +454,15 @@ void DivPlatformYM2610B::acquire_ymfm(short** buf, size_t len) {
     if (!writes.empty()) {
       if (--delay<1 && !(fm->read(0)&0x80)) {
         QueuedWrite& w=writes.front();
-        fm->write(0x0+((w.addr>>8)<<1),w.addr);
+        if (w.addr==0xfffffffe) {
-        fm->write(0x1+((w.addr>>8)<<1),w.val);
+          delay=w.val;
-        regPool[w.addr&0x1ff]=w.val;
+        } else {
+          fm->write(0x0+((w.addr>>8)<<1),w.addr);
+          fm->write(0x1+((w.addr>>8)<<1),w.val);
+          regPool[w.addr&0x1ff]=w.val;
+          delay=1;
+        }
         writes.pop_front();
-        delay=1;
       }
     }
     
@@ -1024,9 +1031,7 @@ void DivPlatformYM2610B::tick(bool sysTick) {
 
   // hard reset handling
   if (mustHardReset) {
-    for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
+    immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
-      immWrite(0xf0,i&0xff);
-    }
     for (int i=0; i<(psgChanOffs-isCSM); i++) {
       if (i==2 && extMode) continue;
       if ((chan[i].keyOn || chan[i].opMaskChanged) && chan[i].hardReset) {

src/engine/platform/ym2610bext.cpp

@@ -638,9 +638,7 @@ void DivPlatformYM2610BExt::tick(bool sysTick) {
 
     // hard reset handling
     if (mustHardReset) {
-      for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
+      immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
-        immWrite(0xf0,i&0xff);
-      }
       for (int i=0; i<4; i++) {
         if (opChan[i].keyOn && opChan[i].hardReset) {
           // restore SL/RR

src/engine/platform/ym2610ext.cpp

@@ -638,9 +638,7 @@ void DivPlatformYM2610Ext::tick(bool sysTick) {
 
     // hard reset handling
     if (mustHardReset) {
-      for (unsigned int i=hardResetElapsed; i<hardResetCycles; i++) {
+      immWrite(0xfffffffe,hardResetCycles-hardResetElapsed);
-        immWrite(0xf0,i&0xff);
-      }
       for (int i=0; i<4; i++) {
         if (opChan[i].keyOn && opChan[i].hardReset) {
           // restore SL/RR