Add Namco 163 Support
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16 changed files with 1225 additions and 6 deletions
137
src/engine/platform/sound/n163/n163.cpp
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137
src/engine/platform/sound/n163/n163.cpp
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/*
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License: BSD-3-Clause
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see https://github.com/cam900/vgsound_emu/LICENSE for more details
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Copyright holder(s): cam900
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Namco 163 Sound emulation core
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This chip is one of NES mapper with sound expansion, This one is by Namco.
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It has 1 to 8 wavetable channels, All channel registers and waveforms are stored to internal RAM.
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4 bit Waveforms are freely allocatable, and its length is variables; its can be stores many short waveforms or few long waveforms in RAM.
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But waveforms are needs to squash, reallocate to avoid conflict with channel register area, each channel register size is 8 bytes per channels.
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Sound output is time division multiplexed, it's can be captured only single channels output at once. in reason, More activated channels are less sound quality.
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Sound register layout
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Address Bit Description
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7654 3210
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78-7f Channel 0
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78 xxxx xxxx Channel 0 Pitch input bit 0-7
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79 xxxx xxxx Channel 0 Accumulator bit 0-7*
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7a xxxx xxxx Channel 0 Pitch input bit 8-15
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7b xxxx xxxx Channel 0 Accumulator bit 8-15*
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7c xxxx xx-- Channel 0 Waveform length, 256 - (x * 4)
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---- --xx Channel 0 Pitch input bit 16-17
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7d xxxx xxxx Channel 0 Accumulator bit 16-23*
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7e xxxx xxxx Channel 0 Waveform base offset
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xxxx xxx- RAM byte (0 to 127)
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---- ---x RAM nibble
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---- ---0 Low nibble
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---- ---1 High nibble
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7f ---- xxxx Channel 0 Volume
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7f Number of active channels
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7f -xxx ---- Number of active channels
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-000 ---- Channel 0 activated
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-001 ---- Channel 1 activated
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-010 ---- Channel 2 activated
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...
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-110 ---- Channel 6 activated
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-111 ---- Channel 7 activated
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70-77 Channel 1 (Optional if activated)
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68-6f Channel 2 (Optional if activated)
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...
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48-4f Channel 6 (Optional if activated)
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40-47 Channel 7 (Optional if activated)
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Rest of RAM area are for 4 bit Waveform and/or scratchpad.
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Each waveform byte has 2 nibbles packed, fetches LSB first, MSB next.
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---- xxxx 4 bit waveform, LSB
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xxxx ---- Same as above, MSB
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Waveform address: Waveform base offset + Bit 16 to 23 of Accumulator, 1 LSB of result is nibble select, 7 MSB of result is Byte address in RAM.
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Frequency formula:
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Frequency: Pitch input * ((Input clock * 15 * Number of activated voices) / 65536)
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*/
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#include "n163.hpp"
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void n163_core::tick()
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{
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m_out = 0;
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// 0xe000-0xe7ff Disable sound bits (bit 6, bit 0 to 5 are CPU ROM Bank 0x8000-0x9fff select.)
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if (m_disable)
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return;
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// tick per each clock
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const u32 freq = m_ram[m_voice_cycle + 0] | (u32(m_ram[m_voice_cycle + 2]) << 8) | (bitfield<u32>(m_ram[m_voice_cycle + 4], 0, 2) << 16); // 18 bit frequency
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u32 accum = m_ram[m_voice_cycle + 1] | (u32(m_ram[m_voice_cycle + 3]) << 8) | ( u32(m_ram[m_voice_cycle + 5]) << 16); // 24 bit accumulator
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const u16 length = 256 - (m_ram[m_voice_cycle + 4] & 0xfc);
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const u8 addr = m_ram[m_voice_cycle + 6] + bitfield(accum, 16, 8);
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const s16 wave = (bitfield(m_ram[bitfield(addr, 1, 7)], bitfield(addr, 0) << 2, 4) - 8);
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const s16 volume = bitfield(m_ram[m_voice_cycle + 7], 0, 4);
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// accumulate address
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accum = bitfield(accum + freq, 0, 24);
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if (bitfield(accum, 16, 8) >= length)
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accum = bitfield(accum, 0, 18);
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// writeback to register
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m_ram[m_voice_cycle + 1] = bitfield(accum, 0, 8);
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m_ram[m_voice_cycle + 3] = bitfield(accum, 8, 8);
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m_ram[m_voice_cycle + 5] = bitfield(accum, 16, 8);
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// update voice cycle
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m_voice_cycle -= 0x8;
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if (m_voice_cycle < (0x78 - (bitfield(m_ram[0x7f], 4, 3) << 3)))
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m_voice_cycle = 0x78;
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// output 4 bit waveform and volume, multiplexed
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m_out = wave * volume;
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}
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void n163_core::reset()
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{
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// reset this chip
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m_disable = false;
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std::fill(std::begin(m_ram), std::end(m_ram), 0);
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m_voice_cycle = 0x78;
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m_addr_latch.reset();
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m_out = 0;
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}
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// accessor
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void n163_core::addr_w(u8 data)
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{
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// 0xf800-0xffff Sound address, increment
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m_addr_latch.addr = bitfield(data, 0, 7);
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m_addr_latch.incr = bitfield(data, 7);
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}
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void n163_core::data_w(u8 data, bool cpu_access)
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{
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// 0x4800-0x4fff Sound data write
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m_ram[m_addr_latch.addr] = data;
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// address latch increment
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if (cpu_access && m_addr_latch.incr)
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m_addr_latch.addr = bitfield(m_addr_latch.addr + 1, 0, 7);
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}
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u8 n163_core::data_r(bool cpu_access)
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{
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// 0x4800-0x4fff Sound data read
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const u8 ret = m_ram[m_addr_latch.addr];
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// address latch increment
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if (cpu_access && m_addr_latch.incr)
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m_addr_latch.addr = bitfield(m_addr_latch.addr + 1, 0, 7);
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return ret;
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}
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78
src/engine/platform/sound/n163/n163.hpp
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78
src/engine/platform/sound/n163/n163.hpp
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/*
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License: BSD-3-Clause
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see https://github.com/cam900/vgsound_emu/LICENSE for more details
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Copyright holder(s): cam900
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Namco 163 Sound emulation core
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*/
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#include <algorithm>
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#include <memory>
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#ifndef _VGSOUND_EMU_N163_HPP
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#define _VGSOUND_EMU_N163_HPP
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#pragma once
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namespace n163
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{
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typedef unsigned char u8;
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typedef unsigned short u16;
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typedef unsigned int u32;
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typedef signed short s16;
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// get bitfield, bitfield(input, position, len)
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template<typename T> T bitfield(T in, u8 pos, u8 len = 1)
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{
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return (in >> pos) & (len ? (T(1 << len) - 1) : 1);
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}
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};
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using namespace n163;
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class n163_core
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{
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public:
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// accessors, getters, setters
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void addr_w(u8 data);
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void data_w(u8 data, bool cpu_access = false);
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u8 data_r(bool cpu_access = false);
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void set_disable(bool disable) { m_disable = disable; }
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// internal state
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void reset();
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void tick();
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// sound output pin
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s16 out() { return m_out; }
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// register pool
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u8 reg(u8 addr) { return m_ram[addr & 0x7f]; }
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private:
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// Address latch
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struct addr_latch_t
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{
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addr_latch_t()
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: addr(0)
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, incr(0)
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{ };
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void reset()
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{
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addr = 0;
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incr = 0;
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}
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u8 addr : 7;
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u8 incr : 1;
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};
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bool m_disable = false;
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u8 m_ram[0x80] = {0}; // internal 128 byte RAM
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u8 m_voice_cycle = 0x78; // Voice cycle for processing
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addr_latch_t m_addr_latch; // address latch
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s16 m_out = 0; // output
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};
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#endif
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