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@ -357,8 +357,11 @@ void es5504_core::regs_w(u8 page, u8 address, u16 data, bool cpu_access)
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if (bitfield(m_adc, 0)) // Writam_ble ADC
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{
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m_adc = (m_adc & 7) | (data & ~7);
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if (cpu_access)
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{
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m_intf.adc_w(m_adc & ~7);
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}
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}
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m_adc = (m_adc & ~3) | (data & 3);
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break;
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case 13: // ACT (Number of voices)
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@ -319,7 +319,7 @@ void es5505_core::host_w(u8 address, u16 data)
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m_hd = data;
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if (m_e.rising_edge())
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{ // update directly
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write(m_ha, m_hd, true);
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write(m_ha, m_hd);
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}
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else
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{
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@ -330,9 +330,9 @@ void es5505_core::host_w(u8 address, u16 data)
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u16 es5505_core::read(u8 address, bool cpu_access) { return regs_r(m_page, address, cpu_access); }
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void es5505_core::write(u8 address, u16 data, bool cpu_access)
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void es5505_core::write(u8 address, u16 data)
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{
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regs_w(m_page, address, data, cpu_access);
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regs_w(m_page, address, data);
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}
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u16 es5505_core::regs_r(u8 page, u8 address, bool cpu_access)
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@ -488,7 +488,7 @@ u16 es5505_core::regs_r(u8 page, u8 address, bool cpu_access)
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return ret;
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}
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void es5505_core::regs_w(u8 page, u8 address, u16 data, bool cpu_access)
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void es5505_core::regs_w(u8 page, u8 address, u16 data)
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{
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address = bitfield(address, 0, 4); // 4 bit address for CPU access
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@ -262,10 +262,10 @@ class es5505_core : public es550x_shared_core
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// bypass chips host interface for debug purpose only
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u16 read(u8 address, bool cpu_access = false);
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void write(u8 address, u16 data, bool cpu_access = false);
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void write(u8 address, u16 data);
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u16 regs_r(u8 page, u8 address, bool cpu_access = false);
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void regs_w(u8 page, u8 address, u16 data, bool cpu_access = false);
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void regs_w(u8 page, u8 address, u16 data);
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u16 regs_r(u8 page, u8 address)
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{
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@ -438,7 +438,7 @@ void es5506_core::host_w(u8 address, u8 data)
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m_hd = data;
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if (m_e.rising_edge())
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{ // update directly
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write(m_ha, m_hd, true);
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write(m_ha, m_hd);
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}
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else
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{
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@ -464,7 +464,7 @@ u8 es5506_core::read(u8 address, bool cpu_access)
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return bitfield(m_read_latch, 24, 8);
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}
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void es5506_core::write(u8 address, u8 data, bool cpu_access)
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void es5506_core::write(u8 address, u8 data)
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{
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const u8 byte = bitfield(address, 0, 2); // byte select
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const u8 shift = 24 - (byte << 3);
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@ -478,7 +478,7 @@ void es5506_core::write(u8 address, u8 data, bool cpu_access)
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return;
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}
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regs_w(m_page, address, m_write_latch, cpu_access);
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regs_w(m_page, address, m_write_latch);
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// Reset latch
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m_write_latch = 0;
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@ -707,7 +707,7 @@ u32 es5506_core::regs_r(u8 page, u8 address, bool cpu_access)
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return read_latch;
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}
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void es5506_core::regs_w(u8 page, u8 address, u32 data, bool cpu_access)
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void es5506_core::regs_w(u8 page, u8 address, u32 data)
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{
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// Global registers
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if (address >= 13)
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@ -329,10 +329,10 @@ class es5506_core : public es550x_shared_core
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// bypass chips host interface for debug purpose only
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u8 read(u8 address, bool cpu_access = false);
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void write(u8 address, u8 data, bool cpu_access = false);
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void write(u8 address, u8 data);
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u32 regs_r(u8 page, u8 address, bool cpu_access = false);
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void regs_w(u8 page, u8 address, u32 data, bool cpu_access = false);
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void regs_w(u8 page, u8 address, u32 data);
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u8 regs8_r(u8 page, u8 address)
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{
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@ -15,7 +15,7 @@ void k053260_core::tick()
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{
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for (int i = 0; i < 4; i++)
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{
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m_voice[i].tick(i);
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m_voice[i].tick();
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m_out[0] += m_voice[i].out(0);
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m_out[1] += m_voice[i].out(1);
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}
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@ -36,7 +36,7 @@ void k053260_core::tick()
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m_dac.set_clock(bitfield(dac_clock, 0, 4));
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}
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void k053260_core::voice_t::tick(u8 ne)
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void k053260_core::voice_t::tick()
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{
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if (m_enable && m_busy)
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{
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@ -61,7 +61,7 @@ class k053260_core : public vgsound_emu_core
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// internal state
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void reset();
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void tick(u8 ne);
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void tick();
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// accessors
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void write(u8 address, u8 data);
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