Sync with master

This commit is contained in:
cam900 2022-09-17 13:33:21 +09:00
parent 146da2ce76
commit 5af02d068e
7 changed files with 19 additions and 16 deletions

View file

@ -357,8 +357,11 @@ void es5504_core::regs_w(u8 page, u8 address, u16 data, bool cpu_access)
if (bitfield(m_adc, 0)) // Writam_ble ADC
{
m_adc = (m_adc & 7) | (data & ~7);
if (cpu_access)
{
m_intf.adc_w(m_adc & ~7);
}
}
m_adc = (m_adc & ~3) | (data & 3);
break;
case 13: // ACT (Number of voices)

View file

@ -319,7 +319,7 @@ void es5505_core::host_w(u8 address, u16 data)
m_hd = data;
if (m_e.rising_edge())
{ // update directly
write(m_ha, m_hd, true);
write(m_ha, m_hd);
}
else
{
@ -330,9 +330,9 @@ void es5505_core::host_w(u8 address, u16 data)
u16 es5505_core::read(u8 address, bool cpu_access) { return regs_r(m_page, address, cpu_access); }
void es5505_core::write(u8 address, u16 data, bool cpu_access)
void es5505_core::write(u8 address, u16 data)
{
regs_w(m_page, address, data, cpu_access);
regs_w(m_page, address, data);
}
u16 es5505_core::regs_r(u8 page, u8 address, bool cpu_access)
@ -488,7 +488,7 @@ u16 es5505_core::regs_r(u8 page, u8 address, bool cpu_access)
return ret;
}
void es5505_core::regs_w(u8 page, u8 address, u16 data, bool cpu_access)
void es5505_core::regs_w(u8 page, u8 address, u16 data)
{
address = bitfield(address, 0, 4); // 4 bit address for CPU access

View file

@ -262,10 +262,10 @@ class es5505_core : public es550x_shared_core
// bypass chips host interface for debug purpose only
u16 read(u8 address, bool cpu_access = false);
void write(u8 address, u16 data, bool cpu_access = false);
void write(u8 address, u16 data);
u16 regs_r(u8 page, u8 address, bool cpu_access = false);
void regs_w(u8 page, u8 address, u16 data, bool cpu_access = false);
void regs_w(u8 page, u8 address, u16 data);
u16 regs_r(u8 page, u8 address)
{

View file

@ -438,7 +438,7 @@ void es5506_core::host_w(u8 address, u8 data)
m_hd = data;
if (m_e.rising_edge())
{ // update directly
write(m_ha, m_hd, true);
write(m_ha, m_hd);
}
else
{
@ -464,7 +464,7 @@ u8 es5506_core::read(u8 address, bool cpu_access)
return bitfield(m_read_latch, 24, 8);
}
void es5506_core::write(u8 address, u8 data, bool cpu_access)
void es5506_core::write(u8 address, u8 data)
{
const u8 byte = bitfield(address, 0, 2); // byte select
const u8 shift = 24 - (byte << 3);
@ -478,7 +478,7 @@ void es5506_core::write(u8 address, u8 data, bool cpu_access)
return;
}
regs_w(m_page, address, m_write_latch, cpu_access);
regs_w(m_page, address, m_write_latch);
// Reset latch
m_write_latch = 0;
@ -707,7 +707,7 @@ u32 es5506_core::regs_r(u8 page, u8 address, bool cpu_access)
return read_latch;
}
void es5506_core::regs_w(u8 page, u8 address, u32 data, bool cpu_access)
void es5506_core::regs_w(u8 page, u8 address, u32 data)
{
// Global registers
if (address >= 13)

View file

@ -329,10 +329,10 @@ class es5506_core : public es550x_shared_core
// bypass chips host interface for debug purpose only
u8 read(u8 address, bool cpu_access = false);
void write(u8 address, u8 data, bool cpu_access = false);
void write(u8 address, u8 data);
u32 regs_r(u8 page, u8 address, bool cpu_access = false);
void regs_w(u8 page, u8 address, u32 data, bool cpu_access = false);
void regs_w(u8 page, u8 address, u32 data);
u8 regs8_r(u8 page, u8 address)
{

View file

@ -15,7 +15,7 @@ void k053260_core::tick()
{
for (int i = 0; i < 4; i++)
{
m_voice[i].tick(i);
m_voice[i].tick();
m_out[0] += m_voice[i].out(0);
m_out[1] += m_voice[i].out(1);
}
@ -36,7 +36,7 @@ void k053260_core::tick()
m_dac.set_clock(bitfield(dac_clock, 0, 4));
}
void k053260_core::voice_t::tick(u8 ne)
void k053260_core::voice_t::tick()
{
if (m_enable && m_busy)
{

View file

@ -61,7 +61,7 @@ class k053260_core : public vgsound_emu_core
// internal state
void reset();
void tick(u8 ne);
void tick();
// accessors
void write(u8 address, u8 data);