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dev167 - fix TL macro

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previously, 127 mapped to TL 0
but now 127 maps to TL 127

yeah, the graph will look inverted I know...
This commit is contained in:
tildearrow 2023-08-21 23:57:07 -05:00
parent b35235b82e
commit 54934dcfc9
16 changed files with 32 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/engine/platform/arcade.cpp
View file

@ -299,7 +299,7 @@ void DivPlatformArcade::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (!op.enable) {
rWrite(baseAddr+ADDR_TL,127);
} else if (KVS(i,j)) {

2
src/engine/platform/genesis.cpp
View file

@ -473,7 +473,7 @@ void DivPlatformGenesis::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (isMuted[i] || !op.enable) {
rWrite(baseAddr+ADDR_TL,127);
} else {

2
src/engine/platform/genesisext.cpp
View file

@ -599,7 +599,7 @@ void DivPlatformGenesisExt::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (isOpMuted[i]) {
rWrite(baseAddr+ADDR_TL,127);
} else {

2
src/engine/platform/opl.cpp
View file

@ -436,7 +436,7 @@ void DivPlatformOPL::tick(bool sysTick) {
}
if (m.tl.had) {
op.tl=63-m.tl.val;
op.tl=m.tl.val&63;
}
if (m.ksl.had) {
op.ksl=m.ksl.val;

2
src/engine/platform/opll.cpp
View file

@ -195,7 +195,7 @@ void DivPlatformOPLL::tick(bool sysTick) {
rWrite(0x06+j,(op.sl<<4)|(op.rr));
}
if (m.tl.had) {
op.tl=((j==1)?15:63)-m.tl.val;
op.tl=m.tl.val&((j==1)?15:63);
if (j==1) {
if (i<9) {
rWrite(0x30+i,((15-VOL_SCALE_LOG_BROKEN(chan[i].outVol,15-chan[i].state.op[1].tl,15))&15)|(chan[i].state.opllPreset<<4));

2
src/engine/platform/tx81z.cpp
View file

@ -262,7 +262,7 @@ void DivPlatformTX81Z::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (isMuted[i] || !op.enable) {
rWrite(baseAddr+ADDR_TL,127);
} else {

2
src/engine/platform/ym2203.cpp
View file

@ -402,7 +402,7 @@ void DivPlatformYM2203::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (isMuted[i] || !op.enable) {
rWrite(baseAddr+ADDR_TL,127);
} else {

2
src/engine/platform/ym2203ext.cpp
View file

@ -502,7 +502,7 @@ void DivPlatformYM2203Ext::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (isOpMuted[i]) {
rWrite(baseAddr+ADDR_TL,127);
} else {

2
src/engine/platform/ym2608.cpp
View file

@ -606,7 +606,7 @@ void DivPlatformYM2608::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (isMuted[i] || !op.enable) {
rWrite(baseAddr+ADDR_TL,127);
} else {

2
src/engine/platform/ym2608ext.cpp
View file

@ -549,7 +549,7 @@ void DivPlatformYM2608Ext::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (isOpMuted[i]) {
rWrite(baseAddr+ADDR_TL,127);
} else {

2
src/engine/platform/ym2610.cpp
View file

@ -539,7 +539,7 @@ void DivPlatformYM2610::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (isMuted[i] || !op.enable) {
rWrite(baseAddr+ADDR_TL,127);
} else {

2
src/engine/platform/ym2610b.cpp
View file

@ -606,7 +606,7 @@ void DivPlatformYM2610B::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (isMuted[i] || !op.enable) {
rWrite(baseAddr+ADDR_TL,127);
} else {

2
src/engine/platform/ym2610bext.cpp
View file

@ -544,7 +544,7 @@ void DivPlatformYM2610BExt::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (isOpMuted[i]) {
rWrite(baseAddr+ADDR_TL,127);
} else {

2
src/engine/platform/ym2610ext.cpp
View file

@ -544,7 +544,7 @@ void DivPlatformYM2610Ext::tick(bool sysTick) {
rWrite(baseAddr+ADDR_SL_RR,(op.rr&15)|(op.sl<<4));
}
if (m.tl.had) {
op.tl=127-m.tl.val;
op.tl=m.tl.val;
if (isOpMuted[i]) {
rWrite(baseAddr+ADDR_TL,127);
} else {