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OPLL: 90%

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effects implemented.
TODO:
- FM macros
- muting
- proper drum mode
- proper VRC7
This commit is contained in:
tildearrow 2022-02-28 03:17:33 -05:00
parent e5c993eb14
commit 539182e643
2 changed files with 34 additions and 30 deletions
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60
src/engine/platform/opll.cpp
View file

@ -507,52 +507,56 @@ int DivPlatformOPLL::dispatch(DivCommand c) {
chan[c.chan].freqChanged=true; chan[c.chan].freqChanged=true;
break; break;
} }
/*
case DIV_CMD_FM_FB: { case DIV_CMD_FM_FB: {
DivInstrumentFM::Operator& mod=chan[c.chan].state.op[0];
//DivInstrumentFM::Operator& car=chan[c.chan].state.op[1];
chan[c.chan].state.fb=c.value&7; chan[c.chan].state.fb=c.value&7;
rWrite(chanOffs[c.chan]+ADDR_FB_ALG,(chan[c.chan].state.alg&7)|(chan[c.chan].state.fb<<3)); rWrite(0x03,(mod.ksl<<6)|((chan[c.chan].state.fms&1)<<4)|((chan[c.chan].state.ams&1)<<3)|chan[c.chan].state.fb);
break; break;
} }
case DIV_CMD_FM_MULT: { case DIV_CMD_FM_MULT: {
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]]; if (c.value==0) {
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]]; DivInstrumentFM::Operator& mod=chan[c.chan].state.op[0];
op.mult=c.value2&15; mod.mult=c.value2&15;
rWrite(baseAddr+ADDR_MULT_DT,(op.mult&15)|(dtTable[op.dt&7]<<4)); rWrite(0x00,(mod.am<<7)|(mod.vib<<6)|((mod.ssgEnv&8)<<2)|(mod.ksr<<4)|(mod.mult));
} else {
DivInstrumentFM::Operator& car=chan[c.chan].state.op[1];
car.mult=c.value2&15;
rWrite(0x30+c.chan,(15-(chan[c.chan].outVol*(15-chan[c.chan].state.op[1].tl))/15)|(chan[c.chan].state.opllPreset<<4));
}
break; break;
} }
case DIV_CMD_FM_TL: { case DIV_CMD_FM_TL: {
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]]; if (c.value==0) {
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]]; DivInstrumentFM::Operator& mod=chan[c.chan].state.op[0];
op.tl=c.value2; DivInstrumentFM::Operator& car=chan[c.chan].state.op[1];
if (isMuted[c.chan]) { mod.tl=c.value2&63;
rWrite(baseAddr+ADDR_TL,127); rWrite(0x02,(car.ksl<<6)|(mod.tl&63));
} else { } else {
if (isOutput[chan[c.chan].state.alg][c.value]) { DivInstrumentFM::Operator& car=chan[c.chan].state.op[1];
rWrite(baseAddr+ADDR_TL,127-(((127-op.tl)*(chan[c.chan].outVol&0x7f))/127)); car.tl=c.value2&15;
} else { rWrite(0x01,(car.am<<7)|(car.vib<<6)|((car.ssgEnv&8)<<2)|(car.ksr<<4)|(car.mult));
rWrite(baseAddr+ADDR_TL,op.tl);
}
} }
break; break;
} }
case DIV_CMD_FM_AR: { case DIV_CMD_FM_AR: {
DivInstrumentFM::Operator& mod=chan[c.chan].state.op[0];
DivInstrumentFM::Operator& car=chan[c.chan].state.op[1];
if (c.value<0) { if (c.value<0) {
for (int i=0; i<4; i++) { mod.ar=c.value2&15;
DivInstrumentFM::Operator& op=chan[c.chan].state.op[i]; car.ar=c.value2&15;
op.ar=c.value2&31;
unsigned short baseAddr=chanOffs[c.chan]|opOffs[i];
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.rs<<6));
}
} else { } else {
DivInstrumentFM::Operator& op=chan[c.chan].state.op[orderedOps[c.value]]; if (c.value==0) {
op.ar=c.value2&31; mod.ar=c.value2&15;
unsigned short baseAddr=chanOffs[c.chan]|opOffs[orderedOps[c.value]]; } else {
rWrite(baseAddr+ADDR_RS_AR,(op.ar&31)|(op.rs<<6)); car.ar=c.value2&15;
}
} }
rWrite(0x04,(mod.ar<<4)|(mod.dr));
rWrite(0x05,(car.ar<<4)|(car.dr));
break; break;
} }
*/
case DIV_ALWAYS_SET_VOLUME: case DIV_ALWAYS_SET_VOLUME:
return 0; return 0;
break; break;

4
src/engine/platform/opll.h
View file

@ -57,8 +57,8 @@ class DivPlatformOPLL: public DivDispatch {
vol(0), vol(0),
pan(3) {} pan(3) {}
}; };
Channel chan[9]; Channel chan[11];
bool isMuted[9]; bool isMuted[11];
struct QueuedWrite { struct QueuedWrite {
unsigned short addr; unsigned short addr;
unsigned char val; unsigned char val;