diff --git a/src/engine/platform/opl.cpp b/src/engine/platform/opl.cpp
index 5411bf298..dcda2908d 100644
--- a/src/engine/platform/opl.cpp
+++ b/src/engine/platform/opl.cpp
@@ -661,6 +661,108 @@ void DivPlatformOPL::acquire_nukedLLE2(short** buf, size_t len) {
 }
 
 void DivPlatformOPL::acquire_nukedLLE3(short** buf, size_t len) {
+  int chOut[20];
+
+  for (size_t h=0; h<len; h++) {
+    //int curCycle=0;
+    //unsigned char subCycle=0;
+
+    for (int i=0; i<20; i++) {
+      chOut[i]=0;
+    }
+    
+    while (true) {
+      lastSH=fm_lle3.o_smpac;
+      lastSH2=fm_lle3.o_smpbd;
+      lastSY=fm_lle3.o_sy;
+
+      // register control
+      if (waitingBusy) {
+        if (delay<62) {
+          fm_lle3.input.cs=0;
+          fm_lle3.input.rd=0;
+          fm_lle3.input.wr=1;
+          fm_lle3.input.address=0;
+        }
+      } else {
+        if (!writes.empty()) {
+          QueuedWrite& w=writes.front();
+
+          if (w.addrOrVal) {
+            regPool[w.addr&511]=w.val;
+            fm_lle3.input.cs=0;
+            fm_lle3.input.rd=1;
+            fm_lle3.input.wr=0;
+            fm_lle3.input.address=(w.addr&0x100)?3:1;
+            fm_lle3.input.data_i=w.val;
+            writes.pop();
+            delay=64;
+          } else {
+            fm_lle3.input.cs=0;
+            fm_lle3.input.rd=1;
+            fm_lle3.input.wr=0;
+            fm_lle3.input.address=(w.addr&0x100)?2:0;
+            fm_lle3.input.data_i=w.addr&0xff;
+            w.addrOrVal=true;
+            // weird. wasn't it 12?
+            delay=64;
+          }
+
+          waitingBusy=true;
+        }
+      }
+
+      fm_lle3.input.mclk=1;
+      FMOPL3_Clock(&fm_lle3);
+      fm_lle3.input.mclk=0;
+      FMOPL3_Clock(&fm_lle3);
+
+      if (waitingBusy) {
+        if (--delay<0) waitingBusy=false;
+      }
+
+      /*if (!(++subCycle&3)) {
+        // TODO: chan osc
+        curCycle++;
+      }*/
+
+      if (fm_lle3.o_sy && !lastSY) {
+        dacVal>>=1;
+        dacVal|=(fm_lle3.o_doab&1)<<17;
+        dacVal2>>=1;
+        dacVal2|=(fm_lle3.o_docd&1)<<17;
+      }
+
+      if (!fm_lle3.o_smpbd && lastSH2) {
+        dacOut3[0]=((dacVal>>1)&0xffff)-0x8000;
+        dacOut3[2]=((dacVal2>>1)&0xffff)-0x8000;
+      }
+
+      if (!fm_lle3.o_smpac && lastSH) {
+        dacOut3[1]=((dacVal>>1)&0xffff)-0x8000;
+        dacOut3[3]=((dacVal2>>1)&0xffff)-0x8000;
+        break;
+      }
+    }
+
+    for (int i=0; i<20; i++) {
+      if (i>=15 && properDrums) {
+        chOut[i]<<=1;
+      } else {
+        chOut[i]<<=2;
+      }
+      if (chOut[i]<-32768) chOut[i]=-32768;
+      if (chOut[i]>32767) chOut[i]=32767;
+      oscBuf[i]->data[oscBuf[i]->needle++]=chOut[i];
+    }
+
+    for (int i=0; i<MIN(4,totalOutputs); i++) {
+      if (dacOut3[i]<-32768) dacOut3[i]=-32768;
+      if (dacOut3[i]>32767) dacOut3[i]=32767;
+
+      buf[i][h]=dacOut3[i];
+    }
+  }
 }
 
 void DivPlatformOPL::acquire(short** buf, size_t len) {
@@ -2015,27 +2117,43 @@ void DivPlatformOPL::reset() {
   memset(regPool,0,512);
 
   dacVal=0;
+  dacVal2=0;
   dacOut=0;
+  dacOut3[0]=0;
+  dacOut3[1]=0;
+  dacOut3[2]=0;
+  dacOut3[3]=0;
   lastSH=false;
+  lastSH2=false;
   lastSY=false;
   waitingBusy=true;
   
   const unsigned int downsampledRate=(unsigned int)((double)rate*round(COLOR_NTSC/72.0)/(double)chipRateBase);
   
   if (emuCore==2) {
-    // reset 2
-    memset(&fm_lle2,0,sizeof(fmopl2_t));
-    fm_lle2.input.ic=0;
-    for (int i=0; i<80; i++) {
-      fm_lle2.input.mclk=1;
-      FMOPL2_Clock(&fm_lle2);
-      fm_lle2.input.mclk=0;
-      FMOPL2_Clock(&fm_lle2);
+    if (chipType==3 || chipType==759 || chipType==4) {
+      // reset 3
+      memset(&fm_lle3,0,sizeof(fmopl3_t));
+      fm_lle3.input.ic=0;
+      for (int i=0; i<400; i++) {
+        fm_lle3.input.mclk=1;
+        FMOPL3_Clock(&fm_lle3);
+        fm_lle3.input.mclk=0;
+        FMOPL3_Clock(&fm_lle3);
+      }
+      fm_lle3.input.ic=1;
+    } else {
+      // reset 2
+      memset(&fm_lle2,0,sizeof(fmopl2_t));
+      fm_lle2.input.ic=0;
+      for (int i=0; i<80; i++) {
+        fm_lle2.input.mclk=1;
+        FMOPL2_Clock(&fm_lle2);
+        fm_lle2.input.mclk=0;
+        FMOPL2_Clock(&fm_lle2);
+      }
+      fm_lle2.input.ic=1;
     }
-    fm_lle2.input.ic=1;
-
-    // reset 3
-    memset(&fm_lle3,0,sizeof(fmopl3_t));
   } else if (emuCore==1) {
     switch (chipType) {
       case 1:
diff --git a/src/engine/platform/opl.h b/src/engine/platform/opl.h
index fa30e97f3..c4346a21e 100644
--- a/src/engine/platform/opl.h
+++ b/src/engine/platform/opl.h
@@ -75,8 +75,11 @@ class DivPlatformOPL: public DivDispatch {
     FixedQueue<QueuedWrite,2048> writes;
 
     unsigned int dacVal;
+    unsigned int dacVal2;
     int dacOut;
+    int dacOut3[4];
     bool lastSH;
+    bool lastSH2;
     bool lastSY;
     bool waitingBusy;