Fix some ES5506 VGM write feature (but still incomplete)
8 bit addWrite because ES5506 host interface is 8 bit width.
This commit is contained in:
cam900
parent
4d7945f778
commit
205e2124b6
4 changed files with 162 additions and 70 deletions
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@ -27,29 +27,124 @@
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#define rWrite(a,...) {if(!skipRegisterWrites) {hostIntf32.push_back(QueuedHostIntf(4,(a),__VA_ARGS__)); }}
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#define immWrite(a,...) {hostIntf32.push_back(QueuedHostIntf(4,(a),__VA_ARGS__));}
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#define pageWrite(p,a,...) \
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#define pageWrite(p,a,d) \
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if (!skipRegisterWrites) { \
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if (curPage!=(p)) { \
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curPage=(p); \
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rWrite(0xf,curPage); \
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rWrite(0xf,curPage) \
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if (dumpWrites) { \
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addWrite(0x3c,0) \
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addWrite(0x3d,0) \
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addWrite(0x3e,0) \
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addWrite(0x3f,curPage) \
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} \
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} \
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rWrite((a),(d)) \
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if (dumpWrites) { \
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addWrite(((a)<<2)|0,((d)>>24)&0xff) \
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addWrite(((a)<<2)|1,((d)>>16)&0xff) \
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addWrite(((a)<<2)|2,((d)>>8)&0xff) \
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addWrite(((a)<<2)|3,((d)>>0)&0xff) \
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} \
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rWrite((a),__VA_ARGS__); \
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}
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#define pageWriteMask(p,pm,a,...) \
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#define pageWriteDelayed(p,a,d,dl) \
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if (!skipRegisterWrites) { \
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if (curPage!=(p)) { \
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curPage=(p); \
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rWrite(0xf,curPage) \
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if (dumpWrites) { \
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addWrite(0x3c,0) \
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addWrite(0x3d,0) \
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addWrite(0x3e,0) \
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addWrite(0x3f,curPage) \
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} \
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} \
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rWrite((a),(d),(dl)) \
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if (dumpWrites) { \
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addWrite(((a)<<2)|0,((d)>>24)&0xff) \
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addWrite(((a)<<2)|1,((d)>>16)&0xff) \
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addWrite(((a)<<2)|2,((d)>>8)&0xff) \
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addWrite(((a)<<2)|3,((d)>>0)&0xff) \
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} \
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}
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#define pageWriteMask(p,pm,a,d) \
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if (!skipRegisterWrites) { \
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if ((curPage&(pm))!=((p)&(pm))) { \
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curPage=(curPage&~(pm))|((p)&(pm)); \
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rWrite(0xf,curPage,(pm)); \
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rWrite(0xf,curPage,(pm)) \
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if (dumpWrites) { \
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addWrite(0x3c,0) \
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addWrite(0x3d,0) \
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addWrite(0x3e,0) \
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addWrite(0x3f,curPage) \
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} \
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} \
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rWrite((a),(d)) \
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if (dumpWrites) { \
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addWrite(((a)<<2)|0,((d)>>24)&0xff) \
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addWrite(((a)<<2)|1,((d)>>16)&0xff) \
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addWrite(((a)<<2)|2,((d)>>8)&0xff) \
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addWrite(((a)<<2)|3,((d)>>0)&0xff) \
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} \
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}
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#define crWrite(c,d) \
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if (!skipRegisterWrites) { \
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if ((curPage&0x5f)!=((c)&0x5f)) { \
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curPage=(curPage&~0x5f)|((c)&0x5f); \
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rWrite(0xf,curPage,0x5f) \
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if (dumpWrites) { \
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addWrite(0x3c,0) \
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addWrite(0x3d,0) \
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addWrite(0x3e,0) \
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addWrite(0x3f,curPage) \
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} \
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} \
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chan[c].cr=(d); \
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rWrite(0,chan[c].cr) \
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if (dumpWrites) { \
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addWrite(0x0,0) \
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addWrite(0x1,0) \
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addWrite(0x2,(chan[c].cr>>8)&0xff) \
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addWrite(0x3,(chan[c].cr>>0)&0xff) \
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} \
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}
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#define crWriteMask(c,d,m) \
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if (!skipRegisterWrites) { \
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if ((curPage&0x5f)!=((c)&0x5f)) { \
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curPage=(curPage&~0x5f)|((c)&0x5f); \
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rWrite(0xf,curPage,0x5f) \
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if (dumpWrites) { \
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addWrite(0x3c,0) \
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addWrite(0x3d,0) \
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addWrite(0x3e,0) \
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addWrite(0x3f,curPage); \
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} \
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} \
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chan[c].cr=(chan[c].cr&~(m))|((d)&(m)); \
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rWrite(0,chan[c].cr,(m)) \
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if (dumpWrites) { \
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addWrite(0x0,0) \
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addWrite(0x1,0) \
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addWrite(0x2,(chan[c].cr>>8)&0xff) \
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addWrite(0x3,(chan[c].cr>>0)&0xff) \
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} \
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rWrite((a),__VA_ARGS__); \
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}
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#define pageReadMask(p,pm,a,st,...) \
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if (!skipRegisterWrites) { \
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if ((curPage&(pm))!=((p)&(pm))) { \
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curPage=(curPage&~(pm))|((p)&(pm)); \
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rWrite(0xf,curPage,(pm)); \
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rWrite(0xf,curPage,(pm)) \
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if (dumpWrites) { \
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addWrite(0x3c,0) \
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addWrite(0x3d,0) \
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addWrite(0x3e,0) \
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addWrite(0x3f,curPage) \
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} \
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} \
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rRead(st,(a),__VA_ARGS__); \
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}
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@ -119,15 +214,15 @@ void DivPlatformES5506::acquire(short** buf, size_t len) {
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while (!hostIntf32.empty()) {
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QueuedHostIntf w=hostIntf32.front();
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if (w.isRead && (w.read!=NULL)) {
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hostIntf8.push(QueuedHostIntf(w.state,0,w.addr,w.read,w.mask));
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hostIntf8.push(QueuedHostIntf(w.state,1,w.addr,w.read,w.mask));
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hostIntf8.push(QueuedHostIntf(w.state,2,w.addr,w.read,w.mask));
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hostIntf8.push(QueuedHostIntf(w.state,3,w.addr,w.read,w.mask,w.delay));
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hostIntf8.push(QueuedHostIntf(w.state,0,w.addr,w.read));
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hostIntf8.push(QueuedHostIntf(w.state,1,w.addr,w.read));
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hostIntf8.push(QueuedHostIntf(w.state,2,w.addr,w.read));
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hostIntf8.push(QueuedHostIntf(w.state,3,w.addr,w.read,w.delay));
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} else {
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hostIntf8.push(QueuedHostIntf(0,w.addr,w.val,w.mask));
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hostIntf8.push(QueuedHostIntf(1,w.addr,w.val,w.mask));
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hostIntf8.push(QueuedHostIntf(2,w.addr,w.val,w.mask));
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hostIntf8.push(QueuedHostIntf(3,w.addr,w.val,w.mask,w.delay));
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hostIntf8.push(QueuedHostIntf(0,w.addr,w.val));
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hostIntf8.push(QueuedHostIntf(1,w.addr,w.val));
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hostIntf8.push(QueuedHostIntf(2,w.addr,w.val));
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hostIntf8.push(QueuedHostIntf(3,w.addr,w.val,w.delay));
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}
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hostIntf32.pop();
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}
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@ -142,24 +237,11 @@ void DivPlatformES5506::acquire(short** buf, size_t len) {
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logE("READING?!");
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hostIntf8.pop();
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} else {
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unsigned int mask=(w.mask>>shift)&0xff;
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if ((mask==0xff) || isMasked) {
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if (mask==0xff) {
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maskedVal=(w.val>>shift)&0xff;
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}
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es5506.host_w((w.addr<<2)+w.step,maskedVal);
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if(dumpWrites) {
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addWrite((w.addr<<2)+w.step,maskedVal);
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}
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isMasked=false;
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if ((w.step==3) && (w.delay>0)) {
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cycle+=w.delay;
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}
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hostIntf8.pop();
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} else if (!isMasked) {
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maskedVal=((w.val>>shift)&mask)|(es5506.host_r((w.addr<<2)+w.step)&~mask);
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isMasked=true;
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es5506.host_w((w.addr<<2)+w.step,(w.val>>shift)&0xff);
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if ((w.step==3) && (w.delay>0)) {
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cycle+=w.delay;
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}
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hostIntf8.pop();
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if (cycle>0) break;
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}
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}
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@ -429,13 +511,13 @@ void DivPlatformES5506::tick(bool sysTick) {
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if (chan[i].pcm.pause!=(bool)(chan[i].std.alg.val&1)) {
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chan[i].pcm.pause=chan[i].std.alg.val&1;
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if (!chan[i].keyOn) {
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pageWriteMask(0x00|i,0x5f,0x00,chan[i].pcm.pause?0x0002:0x0000,0x0002);
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crWriteMask(0x00|i,chan[i].pcm.pause?0x0002:0x0000,0x0002);
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}
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}
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if (chan[i].pcm.direction!=(bool)(chan[i].std.alg.val&2)) {
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chan[i].pcm.direction=chan[i].std.alg.val&2;
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if (!chan[i].keyOn) {
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pageWriteMask(0x00|i,0x5f,0x00,chan[i].pcm.direction?0x0040:0x0000,0x0040);
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crWriteMask(0x00|i,chan[i].pcm.direction?0x0040:0x0000,0x0040);
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}
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}
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}
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@ -469,7 +551,7 @@ void DivPlatformES5506::tick(bool sysTick) {
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}
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}
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if (chan[i].volChanged.ca) {
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pageWriteMask(0x00|i,0x5f,0x00,(chan[i].ca<<10),0x1c00);
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crWriteMask(0x00|i,(chan[i].ca<<10),0x1c00);
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}
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chan[i].volChanged.changed=0;
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}
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@ -578,7 +660,7 @@ void DivPlatformES5506::tick(bool sysTick) {
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break;
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}
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// Set loop mode & Bank
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pageWriteMask(0x00|i,0x5f,0x00,loopFlag,0xe0fd);
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crWriteMask(0x00|i,loopFlag,0xe0fd);
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}
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chan[i].pcmChanged.loopBank=0;
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}
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@ -587,7 +669,7 @@ void DivPlatformES5506::tick(bool sysTick) {
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if (chan[i].filterChanged.changed) {
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if (!chan[i].keyOn) {
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if (chan[i].filterChanged.mode) {
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pageWriteMask(0x00|i,0x5f,0x00,(chan[i].filter.mode<<8),0x0300);
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crWriteMask(0x00|i,(chan[i].filter.mode<<8),0x0300);
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}
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if (chan[i].filterChanged.k2) {
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if (chan[i].std.ex2.mode!=0) { // Relative
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@ -675,11 +757,11 @@ void DivPlatformES5506::tick(bool sysTick) {
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}
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chan[i].k1Prev=0xffff;
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chan[i].k2Prev=0xffff;
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pageWriteMask(0x00|i,0x5f,0x00,0x0303); // Wipeout CR
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crWrite(0x00|i,0x0303); // Wipeout CR
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pageWrite(0x00|i,0x06,0); // Clear ECOUNT
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pageWrite(0x20|i,0x03,startPos); // Set ACCUM to start address
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pageWrite(0x00|i,0x07,0xffff); // Set K1 and K2 to 0xffff
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pageWrite(0x00|i,0x09,0xffff,~0,(chanMax+1)*4*2); // needs to 4 sample period delay
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pageWriteDelayed(0x00|i,0x09,0xffff,(chanMax+1)*4*2); // needs to 4 sample period delay
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pageWrite(0x00|i,0x01,chan[i].freq);
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pageWrite(0x20|i,0x01,(chan[i].pcm.loopMode==DIV_SAMPLE_LOOP_MAX)?chan[i].pcm.start:chan[i].pcm.loopStart);
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pageWrite(0x20|i,0x02,(chan[i].pcm.loopMode==DIV_SAMPLE_LOOP_MAX)?chan[i].pcm.end:chan[i].pcm.loopEnd);
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@ -721,7 +803,7 @@ void DivPlatformES5506::tick(bool sysTick) {
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pageWrite(0x00|i,0x0a,((unsigned char)(chan[i].envelope.k1Ramp)<<8)|(chan[i].envelope.k1Slow?1:0));
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pageWrite(0x00|i,0x08,((unsigned char)(chan[i].envelope.k2Ramp)<<8)|(chan[i].envelope.k2Slow?1:0));
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// initialize filter
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pageWriteMask(0x00|i,0x5f,0x00,(chan[i].pcm.bank<<14)|(chan[i].filter.mode<<8),0xc300);
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crWriteMask(0x00|i,(chan[i].pcm.bank<<14)|(chan[i].filter.mode<<8),0xc300);
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if ((chan[i].std.ex2.mode!=0) && (chan[i].std.ex2.had)) {
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k2=CLAMP(chan[i].filter.k2+chan[i].k2Offs,0,65535);
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} else {
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@ -762,11 +844,11 @@ void DivPlatformES5506::tick(bool sysTick) {
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}
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// Run sample
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pageWrite(0x00|i,0x06,chan[i].envelope.ecount); // Clear ECOUNT
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pageWriteMask(0x00|i,0x5f,0x00,loopFlag,0x3cff);
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crWriteMask(0x00|i,loopFlag,0x3cff);
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}
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}
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if (chan[i].keyOff) {
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pageWriteMask(0x00|i,0x5f,0x00,0x0303); // Wipeout CR
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crWrite(0x00|i,0x0303); // Wipeout CR
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} else if (!chan[i].keyOn && chan[i].active) {
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pageWrite(0x00|i,0x01,chan[i].freq);
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}
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@ -1085,7 +1167,7 @@ int DivPlatformES5506::dispatch(DivCommand c) {
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if (chan[c.chan].active) {
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if (chan[c.chan].pcm.pause!=(bool)(c.value&1)) {
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chan[c.chan].pcm.pause=c.value&1;
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pageWriteMask(0x00|c.chan,0x5f,0x00,chan[c.chan].pcm.pause?0x0002:0x0000,0x0002);
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crWriteMask(0x00|c.chan,chan[c.chan].pcm.pause?0x0002:0x0000,0x0002);
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}
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}
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break;
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@ -1141,7 +1223,7 @@ int DivPlatformES5506::dispatch(DivCommand c) {
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case DIV_CMD_SAMPLE_DIR: {
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if (chan[c.chan].pcm.direction!=(bool)(c.value&1)) {
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chan[c.chan].pcm.direction=c.value&1;
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pageWriteMask(0x00|c.chan,0x5f,0x00,chan[c.chan].pcm.direction?0x0040:0x0000,0x0040);
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crWriteMask(0x00|c.chan,chan[c.chan].pcm.direction?0x0040:0x0000,0x0040);
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}
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break;
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}
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@ -1212,12 +1294,14 @@ void DivPlatformES5506::reset() {
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cycle=0;
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curPage=0;
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maskedVal=0;
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irqv=0x80;
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isMasked=false;
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irqTrigger=false;
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chanMax=initChanMax;
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if (dumpWrites) {
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addWrite(0xffffffff,0);
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}
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pageWriteMask(0x00,0x60,0x0b,chanMax);
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pageWriteMask(0x00,0x60,0x0b,0x1f);
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// set serial output to I2S-ish, 16 bit
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@ -1286,6 +1370,10 @@ unsigned char* DivPlatformES5506::getRegisterPool() {
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for (unsigned char p=0; p<128; p++) {
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for (unsigned char r=0; r<16; r++) {
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unsigned int reg=es5506.regs_r(p,r,false);
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// Sync CR register with register pool
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if (((p&0x40)==0) && (r==0)) {
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chan[p&0x1f].cr=reg&0xffff;
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}
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for (int b=0; b<4; b++) {
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*regPoolPtr++ = reg>>(24-(b<<3));
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}
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