363 lines
8 KiB
C
363 lines
8 KiB
C
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/*
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* Copyright (C) 2022-2023 nukeykt
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*
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* This file is part of YMF276-LLE.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* YMF276/YM3438 emulator.
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* Thanks:
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* John McMaster (siliconpr0n.org):
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* Yamaha YM3438 & YM2610 decap and die shot.
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* org, andkorzh, HardWareMan (emu-russia):
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* help & support, YMF276 and YM2612 decap.
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*
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*/
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#pragma once
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#include <stdint.h>
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enum {
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fmopn2_flags_ym3438 = 1,
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};
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typedef struct {
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int phi;
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int ic;
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} fmopn2_prescaler_input_t;
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typedef struct {
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int phi_phase;
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int ic;
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int rd;
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int wr;
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int cs;
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int address;
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int data;
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int test;
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int i_fsm_reset; // (chip->ic_check_latch[1] & 16) != 0;
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} fmopn2_input_t;
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typedef struct {
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int flags;
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// input
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fmopn2_input_t input_old, input;
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int i_phi1;
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int i_phi2;
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fmopn2_prescaler_input_t pinput, pinput_old;
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// clock
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int ic_latch[2]; // 12
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int ic_check_latch[2]; // 4
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int prescaler_latch[2]; // 6
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int phi1_latch[2];
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int phi2_latch[2];
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int dphi1_latch[4];
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int dphi2_latch[3];
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int dclk1;
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int dclk2;
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int fsm_reset;
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// output
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int dac_val;
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int out_l;
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int out_r;
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// io
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int write_addr_trig;
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int write_addr_trig_sync;
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int write_addr_dlatch;
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int write_addr_sr[2];
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int write_data_trig;
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int write_data_trig_sync;
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int write_data_dlatch;
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int write_data_sr[2];
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int data_latch;
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int bank_latch;
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int busy_cnt[2];
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int busy_latch[2];
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int io_ic_latch[2];
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int write_fm_address[2];
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int fm_address[2];
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int write_fm_data[2];
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int fm_data[2];
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int status_timer_a_dlatch;
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int status_timer_b_dlatch;
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// mode registers
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int write_mode_21[2];
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int write_mode_22[2];
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int write_mode_24[2];
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int write_mode_25[2];
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int write_mode_26[2];
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int write_mode_27[2];
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int write_mode_28[2];
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int write_mode_2a[2];
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int write_mode_2b[2];
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int write_mode_2c[2];
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int mode_test_21[2];
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int mode_lfo_en[2];
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int mode_lfo_freq[2];
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int mode_timer_a_reg[2];
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int mode_timer_b_reg[2];
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int mode_ch3[2];
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int mode_timer_a_load[2];
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int mode_timer_a_enable[2];
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int mode_timer_a_reset[2];
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int mode_timer_b_load[2];
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int mode_timer_b_enable[2];
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int mode_timer_b_reset[2];
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int mode_kon_operator[2];
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int mode_kon_channel[2];
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int mode_dac_data[2];
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int mode_dac_en[2];
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int mode_test_2c[2];
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int mode_kon[4][2];
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// operator registers
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int slot_multi[2][4][2];
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int slot_dt[2][3][2];
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int slot_tl[2][7][2];
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int slot_ar[2][5][2];
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int slot_ks[2][2][2];
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int slot_dr[2][5][2];
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int slot_am[2][1][2];
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int slot_sr[2][5][2];
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int slot_rr[2][4][2];
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int slot_sl[2][4][2];
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int slot_ssg_eg[2][4][2];
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// channel registers
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int chan_fnum[11][2];
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int chan_fnum_ch3[11][2];
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int chan_block[3][2];
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int chan_block_ch3[3][2];
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int chan_a4[2];
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int chan_ac[2];
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int chan_connect[3][2];
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int chan_fb[3][2];
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int chan_pms[3][2];
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int chan_ams[2][2];
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int chan_pan[2][2];
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int reg_cnt1[2];
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int reg_cnt2[2];
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// lfo
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int lfo_cnt1[2];
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int lfo_cnt2[2];
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int lfo_dlatch;
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int lfo_dlatch_load;
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int lfo_inc_latch[2];
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// pg
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int pg_fnum[2][2];
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int pg_kcode[2][2];
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int pg_fnum_lfo1;
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int pg_fnum_lfo2;
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int pg_lfo_shift;
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int pg_lfo_sign;
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int pg_lfo;
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int pg_freq1;
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int pg_freq2;
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int pg_freq3;
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int pg_freq4;
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int pg_freq5[2];
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int pg_freq6;
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int pg_freq_m1;
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int pg_block;
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int pg_dt[2];
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int pg_detune[2];
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int pg_multi[2][2];
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int pg_multi2;
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int pg_inc[2];
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int pg_inc_mask[2];
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int pg_phase[20][2];
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int pg_reset_latch[2];
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int pg_debug[2];
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int pg_reset[2];
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// eg
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int eg_prescaler[2];
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int eg_prescaler_clock_l[2];
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int eg_prescaler_l;
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int eg_clock_delay[2];
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int eg_step[2];
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int eg_timer_load;
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int eg_timer[2];
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int eg_timer_carry[2];
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int eg_timer_mask[2];
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int eg_timer_masked[2];
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int eg_timer_low_lock;
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int eg_shift_lock;
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int eg_level[10][2];
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int eg_level_latch[2];
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int eg_level_latch_inv;
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int eg_state[2][2];
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int eg_ssg_dir[2];
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int eg_ssg_inv[2];
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int eg_ssg_holdup[2];
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int eg_ssg_enable[2];
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int eg_ssg_pgreset[2];
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int eg_ssg_pgrepeat[2];
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int eg_key[2];
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int eg_rate_nonzero[2];
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int eg_rate;
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int eg_ksv;
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int eg_rate2;
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int eg_inc1;
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int eg_inc2;
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int eg_rate12;
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int eg_rate13;
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int eg_rate14;
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int eg_rate15;
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int eg_maxrate[2];
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int eg_incsh0;
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int eg_incsh1;
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int eg_incsh2;
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int eg_incsh3;
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int eg_incsh_nonzero[2];
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int eg_inc_total;
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int eg_level_ssg[2];
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int eg_sl[2][2];
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int eg_nextlevel[2];
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int eg_kon_csm[2];
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int eg_kon_latch[2];
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int eg_tl[2][2];
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int eg_ams;
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int eg_lfo[2];
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int eg_ch3_latch[2];
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int eg_out;
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int eg_out_tl;
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int eg_out_total;
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int eg_debug[2];
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// op
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int op_mod[10][2];
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int op_phase[2];
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int op_logsin_base[2];
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int op_logsin_delta[2];
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int op_logsin_add_delta[2];
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int op_atten[2];
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int op_env[2];
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int op_pow_base[2];
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int op_pow_delta[2];
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int op_pow_add_delta[2];
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int op_shift[2];
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int op_sign[2];
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int op_output[2];
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int op_op1[2][14][2];
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int op_op2[14][2];
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int op_mod_sum[2];
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int op_dofeedback[2];
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// accumulator
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int ch_accm[14][2];
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int ch_out[9][2];
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int ch_out_dlatch;
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int ch_out_pan_dlatch;
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int ch_dac_load;
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int ch_out_debug[2];
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int ch_accm_l[2];
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int ch_accm_r[2];
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// timers
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int timer_dlatch;
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int timer_a_cnt[2];
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int timer_a_load_latch[2];
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int timer_a_load_old[2];
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int timer_a_load_dlatch;
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int timer_a_of[2];
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int timer_a_status[2];
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int timer_b_subcnt[2];
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int timer_b_subcnt_of[2];
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int timer_b_cnt[2];
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int timer_b_load_latch[2];
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int timer_b_load_old[2];
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int timer_b_load_dlatch;
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int timer_b_of[2];
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int timer_b_status[2];
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int timer_csm_key_dlatch;
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// fm algorithm
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int alg_mod_op1_0;
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int alg_mod_op1_1;
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int alg_mod_op2;
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int alg_mod_prev_0;
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int alg_mod_prev_1;
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int alg_output;
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int alg_mod_op1_0_l;
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int alg_mod_op1_1_l;
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int alg_mod_op2_l;
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int alg_mod_prev_0_l;
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int alg_mod_prev_1_l;
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int alg_output_l;
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// fsm
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int fsm_cnt1[2];
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int fsm_cnt2[2];
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// fsm table output
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int fsm_clock_eg;
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int fsm_clock_timers1;
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int fsm_clock_timers;
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int fsm_op4_sel;
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int fsm_op1_sel;
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int fsm_op2_sel;
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int fsm_op3_sel;
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int fsm_sel2;
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int fsm_sel23;
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int fsm_ch3_sel;
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int fsm_dac_load;
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int fsm_dac_out_sel;
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int fsm_dac_ch6;
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// ymf276
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int fsm_clock_eg_l;
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int fsm_op1_sel_l;
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int fsm_sel1_l;
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int fsm_sel2_l;
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int fsm_sel23_l;
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int fsm_ch3_sel_l;
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int fsm_dac_load_l;
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int fsm_dac_out_sel_l;
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int fsm_dac_ch6_l;
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int fsm_lro_l[2];
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int fsm_wco_l[2];
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int fsm_lro_l2[2];
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int fsm_wco_l2[2];
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int fsm_op1_sel_l2[2];
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int fsm_op1_sel_l3[2];
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int fsm_shifter_ctrl[2];
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int fsm_load_l;
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int fsm_load_r;
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int dac_shifter[2];
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int dac_so_l[2];
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int o_bco;
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int o_wco;
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int o_lro;
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int o_so;
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} fmopn2_t;
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int FMOPN2_ReadStatus(fmopn2_t *chip);
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void FMOPN2_Clock(fmopn2_t *chip, int phi);
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