furnace/src/engine/platform/amiga.h

156 lines
4.2 KiB
C
Raw Normal View History

2022-02-14 22:12:20 -05:00
/**
* Furnace Tracker - multi-system chiptune tracker
2023-01-19 19:18:40 -05:00
* Copyright (C) 2021-2023 tildearrow and contributors
2022-02-14 22:12:20 -05:00
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
2022-01-15 17:28:33 -05:00
#ifndef _AMIGA_H
#define _AMIGA_H
2022-01-15 15:50:53 -05:00
#include "../dispatch.h"
#include <queue>
#include "../waveSynth.h"
2022-01-15 15:50:53 -05:00
class DivPlatformAmiga: public DivDispatch {
struct Channel: public SharedChannel<signed char> {
2022-01-15 15:50:53 -05:00
unsigned int audLoc;
unsigned short audLen;
unsigned int audPos;
unsigned int dmaLoc;
unsigned short dmaLen;
2022-01-15 17:28:33 -05:00
int audSub;
2022-01-15 15:50:53 -05:00
signed char audDat;
signed char audDat2;
unsigned char volPos;
2022-01-15 17:28:33 -05:00
int sample, wave;
int busClock;
2023-03-10 04:22:21 -05:00
bool useWave, setPos, useV, useP, dmaOn, audDatClock, writeVol;
DivWaveSynth ws;
2022-01-15 15:50:53 -05:00
Channel():
SharedChannel<signed char>(64),
2022-01-15 15:50:53 -05:00
audLoc(0),
audLen(0),
audPos(0),
dmaLoc(0),
dmaLen(0),
2022-01-15 17:28:33 -05:00
audSub(0),
2022-01-15 15:50:53 -05:00
audDat(0),
audDat2(0),
volPos(0),
2022-01-15 15:50:53 -05:00
sample(-1),
wave(-1),
busClock(0),
2022-01-15 17:28:33 -05:00
useWave(false),
2022-03-14 10:50:52 -04:00
setPos(false),
2022-03-27 01:02:17 -04:00
useV(false),
useP(false),
dmaOn(false),
2023-03-10 04:22:21 -05:00
audDatClock(false),
writeVol(true) {}
2022-01-15 15:50:53 -05:00
};
Channel chan[4];
DivDispatchOscBuffer* oscBuf[4];
2022-01-15 15:50:53 -05:00
bool isMuted[4];
bool bypassLimits;
bool amigaModel;
2022-03-27 00:39:20 -04:00
bool filterOn;
2023-03-09 20:00:15 -05:00
struct Amiga {
// register state
bool audInt[4]; // interrupt on
bool audEn[4]; // audio DMA on
bool useP[4]; // period modulation
2023-03-10 04:22:21 -05:00
bool useV[4]; // volume modulation
bool dmaEn;
2023-03-09 20:00:15 -05:00
unsigned int audLoc[4]; // address
unsigned short audLen[4]; // length
unsigned short audPer[4]; // period
unsigned char audVol[4]; // volume
signed char audDat[2][4]; // data
// internal state
int audTick[4]; // tick of period
unsigned int dmaLoc[4]; // address
2023-03-10 04:22:21 -05:00
unsigned short dmaLen[4]; // position
2023-03-09 20:00:15 -05:00
bool audByte[4]; // which byte of audDat to output
unsigned char volPos; // position of volume PWM
Amiga() {
memset(this,0,sizeof(*this));
}
} amiga;
2022-03-27 00:39:20 -04:00
int filter[2][4];
int filtConst;
int filtConstOff, filtConstOn;
2023-03-09 20:00:15 -05:00
int chipMem, chipMask;
2022-01-15 15:50:53 -05:00
unsigned char volTable[64][64];
unsigned int sampleOff[256];
bool sampleLoaded[256];
2023-03-10 04:22:21 -05:00
unsigned short regPool[256];
unsigned char* sampleMem;
size_t sampleMemLen;
2022-02-04 17:59:55 -05:00
int sep1, sep2;
friend void putDispatchChip(void*,int);
2022-01-27 00:29:16 -05:00
friend void putDispatchChan(void*,int,int);
2023-03-09 20:00:15 -05:00
void irq(int ch);
2023-03-10 04:22:21 -05:00
void rWrite(unsigned short addr, unsigned short val);
void updateWave(int ch);
2023-03-09 20:00:15 -05:00
2022-01-15 15:50:53 -05:00
public:
2023-01-02 04:53:37 -05:00
void acquire(short** buf, size_t len);
2022-01-15 15:50:53 -05:00
int dispatch(DivCommand c);
2022-01-27 00:29:16 -05:00
void* getChanState(int chan);
DivDispatchOscBuffer* getOscBuffer(int chan);
2023-03-10 04:22:21 -05:00
unsigned char* getRegisterPool();
int getRegisterPoolSize();
int getRegisterPoolDepth();
2022-01-15 15:50:53 -05:00
void reset();
void forceIns();
void tick(bool sysTick=true);
2022-01-15 15:50:53 -05:00
void muteChannel(int ch, bool mute);
int getOutputCount();
2022-01-15 15:50:53 -05:00
bool keyOffAffectsArp(int ch);
DivMacroInt* getChanMacroInt(int ch);
void setFlags(const DivConfig& flags);
2022-01-17 23:59:52 -05:00
void notifyInsChange(int ins);
2022-01-18 00:25:10 -05:00
void notifyWaveChange(int wave);
2022-01-15 15:50:53 -05:00
void notifyInsDeletion(void* ins);
void renderSamples(int chipID);
2023-03-10 04:22:21 -05:00
void poke(unsigned int addr, unsigned short val);
void poke(std::vector<DivRegWrite>& wlist);
2022-02-03 18:38:57 -05:00
const char** getRegisterSheet();
const void* getSampleMem(int index=0);
size_t getSampleMemCapacity(int index=0);
size_t getSampleMemUsage(int index=0);
bool isSampleLoaded(int index, int sample);
int init(DivEngine* parent, int channels, int sugRate, const DivConfig& flags);
2022-01-15 15:50:53 -05:00
void quit();
};
#endif